# Logic Design Questions and Answers – Counter Design Using S-R and J-K Flip-Flops

This set of Logic Design Multiple Choice Questions & Answers (MCQs) focuses on “Counter Design Using S-R and J-K Flip-Flops”.

1. For a 4 bit MOD-16 ripple counter using J-K flip-flop, the propagation delay of each flip flop is 50ns. What is the maximum clock frequency can be used?
a) 10 MHz
b) 20 MHz
c) 5 MHz
d) 40 MHz

Explanation: Total propagation delay for 4 flip-flops (1 bit for each) = (4 × 50) = 200ns
So, maximum clock frequency is reciprocal of total propagation delay = (1 / 200 × 10-9) Hz
= 5 × 106 Hz
= 5 MHz

2. What is the minimum number of flip-flops needed to build a MOD-17 up counter?
a) 2
b) 3
c) 4
d) 5

Explanation: The minimum number of flip-flops required to build a MOD-n counter is N such that 2N > n.
To fulfill this criteria, N must be equal to 5 as 24 < 17 and 25 > 17. Hence minimum 5 flip-flops are required.

3. A MOD-16 ripple counter using J-K flip-flop has a current state 1001. What will the state be after 31 clock pulses?
a) 1001
b) 1010
c) 1000
d) 1111

Explanation: A MOD-16 ripple counter counts from 0 to 15. So starting from current binary value 1001 or equivalent decimal value 11, after 31 clock pulses, logically it becomes (11 + 31) = 42. Now, if we divide 42 by 16, a remainder of decimal 10 or binary 1000 is obtained, and that’s the final state after 31 clock pulses.

4. A specific counter is using 5 S-R flip-flops. So what is the maximum number of states possible?
a) 4
b) 16
c) 32
d) 64

Explanation: Maximum number of states possible is given by 2n for a counter with n flip-flops. So, the maximum number of states is 25 = 32.

5. Which input is used to set any counter at any desired state?
a) Preset
b) Clear
c) Clk
d) Input

Explanation: A low signal at the Preset terminals of all the flip flops are required to set the counter value at any desired state. This signal resets the value inside the counter and sets to the desired value. Other option like Clear is used to set the flip-flops to 0, Clk is used to connect to clock pulse, and Input pins are generally set to logic high(1).

6. Which counter counts both increments and decrements?
a) Up Counter
b) Down Counter
c) Ring Counter
d) Up-Down Counter

Explanation: In an Up-Down counter, both the outputs of the flip-flops, Q and Q’ are used as the input to the next flip-flop and they are selected according to the operation. The selection operation is done by using AND gates. AND gates used for Up operation, take a signal named UP-COUNT and Q from flip-flop as inputs. Similarly, AND gates used for Down operation, takes a signal named DOWN-COUNT and Q’ from flip-flop as inputs. Preferred signal is kept high according to Up/Down operation while the other is kept low.

7. What is the counting range of a BCD counter?
a) 0 to 10
b) 1 to 10
c) 0 to 9
d) 1 to 9

Explanation: A BCD counter is also known as a decade counter or a MOD-10 counter. The BCD code or Binary Coded Decimal code represents every single integer in an equivalent 4-digit binary form. As there are 10 digits, 0-9, so the BCD counter must count from 0 to 9.

8. In a preset table counter using J-K flip flop, what signal is applied to the J and K inputs?
a) Logic 1
b) Logic 0
c) Clock pulse
d) Preset

Explanation: A preset table counter is a type of counter circuit where any randomly desired state can be set as the starting state by the user. Assigning logic 1 to both the inputs of a J-K flip flop takes it to toggle state. This toggle states of the used flip-flops are necessary for the counter operation.

9. How many J-K flip flops are used to design a master slave flip-flop?
a) 1
b) 2
c) 3
d) 4

Explanation: J-K flip-flops are flip-flops those are created by adding two AND gates to the inputs of the S-R latch. Inputs to the AND gates are J and K respectively. Two J-K flip-flops are present in a master-slave flip flop. One master followed by slave. Hence the correct answer is 2.

10. How many NAND gates are required to build a J-K Master Slave Flip-Flop?
a) 4
b) 16
c) 8
d) 2

Explanation: J-K Master-Slave flip-flops are built with two JK flip-flops. The first one is called master and the second one is slave. The master feeds the slave. Again, each JK flip-flop requires 4 NAND gate. Hence a master slave flip-flop will require 4 × 2 = 8 NAND gates.

11. Which one of the following states the forbidden state of SR flip-flop?
a) S = 1, R = 0
b) S = 0, R = 1
c) S = 0, R = 0
d) S = 1, R = 1

Explanation: RS flip-flop is a specific electronic circuit component that is designed generally with NOR gates. The output of the SR flip-flop depends on the inputs such as it gives both the output 0 if both the inputs are logic 1. We know that the two outputs of a flip-flop are complement of each other. Thus they cannot be equal at a same time. Hence S = 1, R = 1 state is stated as forbidden state.

12. Which one of the following states the memory state of SR flip-flop?
a) S = 1, R = 0
b) S = 0, R = 1
c) S = 0, R = 0
d) S = 1, R = 1

Explanation: RS flip-flop is a specific electronic circuit component that is designed generally with NOR gates. The output of the SR flip-flop depends on the inputs such as it doesn’t change its output state if both the inputs are logic 0. Hence it is termed as a memory state.

13. When does a flip-flop change its state?
a) During no clock pulse
b) During falling edge only
c) During rising edge only
d) During rising or falling edge

Explanation: Flip-flops are electronic sequential elements those can be used to store data. Flip-flops are built using basic logic gates like AND, NAND, OR etc. These are edge-triggered elements those use any one of the rising or falling edge of the applied clock pulse for their operation.

14. What does the S and R of an SR flip-flop stand for?
a) Set Reset
b) Send Resend
c) Stop Restart
d) Start Restart

Explanation: SR flip-flops are electronic sequential circuits those are used generally to store data. Here the S stands for set and R stands for R. A S = 1 R = 0 state represents a set state and S = 0 R = 1 state represents reset state.

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