# Logic Design Questions and Answers – Counters for Other Sequences

This set of Logic Design Multiple Choice Questions & Answers (MCQs) focuses on “Counters for Other Sequences”.

1. Write the Verilog code for a synchronous Binary coded Decimal (BCD) up counter with synchronous Active HIGH reset. ‘q’ is the output and ‘clk’ is the clock signal.
a)

```module counter (q, clk, reset);
output reg [3:0] q;
input clk, reset;
always @(posedge clk)
begin
if (reset || (q >= 4’b1001))
q <= 4’b0000;
else
q <= q + 4’b0001;
end
endmodule```

b)

```module counter (q, clk, reset);
output reg [3:0] q;
input clk, reset;
always @(posedge clk)
begin
if (reset && (q >= 4’b1001))
q <= 4’b0000;
else
q <= q + 4’b0001;
end
endmodule```

c)

```module counter (q, clk, reset);
output reg [3:0] q;
input clk, reset;
always @(posedge clk)
begin
if (reset || (q >= 4’b1001))
q <= 4’b0000;
else
q <= q - 4’b0001;
end
endmodule```

d)

```module counter (q, clk, reset);
output reg [3:0] q;
input clk, reset;
always @(posedge clk)
begin
if (reset)
q <= 4’b0000;
else
q <= q + 4’b0001;
end
endmodule```
Explanation: The BCD up counter counts upwards from 0 (4’b0000) to 9 (4’b1001). After 9 it will start again from zero. It will reset to zero on the positive edge of the clock if the reset signal is HIGH. Hence the reset signal is Active HIGH and synchronous.

2. Write the Verilog code for a 4 bit wide ring counter. The counter should be reset to 4’b1000 if reset is asserted. The reset is Active HIGH and synchronous. ‘q’ is the output and ‘clk’ is the clock signal.
a)

```module ring_ctr  #(parameter WIDTH = 4)
(input logic clk,
input logic reset,
output logic [WIDTH-1:0] q);

always @ (posedge clk) begin
if (reset)
q <= 1 << (WIDTH -1);
else begin
q <= q >> 1;
q[WIDTH-1] <= q[0];
end
end
endmodule```

b)

```module ring_ctr  #(parameter WIDTH = 4)
(input logic clk,
input logic reset,
output logic [WIDTH:0] q);

always @ (posedge clk) begin
if (reset)
q <= 1 << (WIDTH);
else begin
q <= q >> 1;
q[WIDTH] <= q[0];
end
end
endmodule```

c)

```module ring_ctr  #(parameter WIDTH = 4)
(input logic clk,
input logic reset,
output logic [WIDTH-1:0] q);

always @ (posedge clk) begin
if (reset)
q <= 1 << (WIDTH -1);
else begin
q <= q + 1;
q[WIDTH-1] <= q[0];
end
end
endmodule```

d)

```module ring_ctr  #(parameter WIDTH = 4)
(input logic clk,
input logic reset,
output logic [WIDTH-1:0] q);

always @ (posedge clk) begin
if (reset)
q <= 1 << (WIDTH -1);
else begin
q <= q >> 1;
q[WIDTH-1] <= q[0];
end
end
endmodule```
Explanation: The 4 bit wide ring counter will start counting from 4’b1000 when reset is asserted. The output of the counter will be unknown initially till the reset is asserted. The reset is Active HIGH and asynchronous. The counter will right shift the bit that is HIGH on the positive edge of the clock. The sequence will be 1000, 0100, 0010, 0001, 1000, 0100 ….

3. Write the Verilog code for a 5 bit wide ring counter. The counter should be reset to 5’b10000 if reset is asserted. The reset is Active HIGH and synchronous. ‘q’ is the output and ‘clk’ is the clock signal.
a)

```module ring_ctr  #(parameter WIDTH = 5)
(input logic clk,
input logic reset,
output logic [WIDTH-1:0] q);

always @ (posedge clk) begin
if (reset)
q <= 1 << (WIDTH -1);
else begin
q <= q >> 1;
q[WIDTH-1] <= q[0];
end
end
endmodule```

b)

```module ring_ctr  #(parameter WIDTH = 5)
(input logic clk,
input logic reset,
output logic [WIDTH:0] q);

always @ (posedge clk) begin
if (reset)
q <= 1 << (WIDTH);
else begin
q <= q >> 1;
q[WIDTH] <= q[0];
end
end
endmodule```

c)

```module ring_ctr  #(parameter WIDTH = 5)
(input logic clk,
input logic reset,
output logic [WIDTH-1:0] q);

always @ (posedge clk) begin
if (reset)
q <= 1 << (WIDTH -1);
else begin
q <= q + 1;
q[WIDTH-1] <= q[0];
end
end
endmodule```

d)

```module ring_ctr  #(parameter WIDTH = 5)
(input logic clk,
input logic reset,
output logic [WIDTH-1:0] q);

always @ (posedge clk) begin
if (reset)
q <= 1 << (WIDTH -1);
else begin
q <= q >> 1;
q[WIDTH-1] <= q[0];
end
end
endmodule```
Explanation: The 5 bit wide ring counter will start counting from 5’b10000 when reset is asserted. The output of the counter will be unknown initially till the reset is asserted. The reset is Active HIGH and asynchronous. The counter will right shift the bit that is HIGH on the positive edge of the clock. The sequence will be 10000, 01000, 00100, 00010, 00001, 10000, 01000 ….

4. Write the Verilog code for a 4 bit Johnson counter. The output is ‘q’, active HIGH synchronous reset signal is ‘reset’ and the clock signal is ‘clk’. Hint: The sequence is 0000, 0001, 0011, 0111, 1111, 1110, 1100, 1000, 0000, 0001…
a)

```module twisted_ring_ctr #(parameter WIDTH = 4)
(input logic clk,
input logic reset,
output logic [WIDTH-1:0] q);

always @ (posedge clk) begin
if (reset)
q <= 0;
else begin
q <= q << 1;
q[0] <= ~q[WIDTH-1];
end
end
endmodule```

b)

```module twisted_ring_ctr #(parameter WIDTH = 4)
(input logic clk,
input logic reset,
output logic [WIDTH:0] q);

always @ (posedge clk) begin
if (reset)
q <= 0;
else begin
q <= q << 1;
q[0] <= ~q[WIDTH];
end
end
endmodule```

c)

```module twisted_ring_ctr #(parameter WIDTH = 4)
(input logic clk, input logic reset,
output logic [WIDTH-1:0] q);

always @ (posedge clk) begin
if (reset)
q <= 0;
else begin
q <= q << 1;
q[0] <= q[WIDTH-1];
end
end
endmodule```

d)

```module twisted_ring_ctr #(parameter WIDTH = 4)
(input logic clk, input logic reset,
output logic [WIDTH-1:0] q);

always @ (posedge clk) begin
if (reset)
q <= 0;
else begin
q <= q + 1;
q[0] <= ~q[WIDTH-1];
end
end
endmodule```
Explanation: A Johnson counter is a variation of the ring counter where the complement of the output of the last stage is fed back to the first stage. The above Johnson counter is 4 bits wide, so the width parameter is 4.

5. Write the Verilog code for a 3 bit Johnson counter. The output is ‘q’, active HIGH synchronous reset signal is ‘reset’ and the clock signal is ‘clk’. Hint: The sequence is 000, 001, 011, 111, 110, 100, 000, 001, 011…
a)

```module twisted_ring_ctr #(parameter WIDTH = 3)
(input logic clk,
input logic reset,
output logic [WIDTH-1:0] q);

always @ (posedge clk) begin
if (reset)
q <= 0;
else begin
q <= q << 1;
q[0] <= ~q[WIDTH-1];
end
end
endmodule```

b)

```module twisted_ring_ctr #(parameter WIDTH = 3)
(input logic clk,
input logic reset,
output logic [WIDTH:0] q);

always @ (posedge clk) begin
if (reset)
q <= 0;
else begin
q <= q << 1;
q[0] <= ~q[WIDTH];
end
end
endmodule```

c)

```module twisted_ring_ctr #(parameter WIDTH = 3)
(input logic clk, input logic reset,
output logic [WIDTH-1:0] q);

always @ (posedge clk) begin
if (reset)
q <= 0;
else begin
q <= q << 1;
q[0] <= q[WIDTH-1];
end
end
endmodule```

d)

```module twisted_ring_ctr #(parameter WIDTH = 3)
(input logic clk, input logic reset,
output logic [WIDTH-1:0] q);

always @ (posedge clk) begin
if (reset)
q <= 0;
else begin
q <= q + 1;
q[0] <= ~q[WIDTH-1];
end
end
endmodule```
Explanation: A Johnson counter is a variation of the ring counter where the complement of the output of the last stage is fed back to the first stage. The above Johnson counter is 3 bits wide, so the width parameter is 3.

6. Write the Verilog code for a 2 bit Johnson counter. The output is ‘q’, active HIGH synchronous reset signal is ‘reset’ and the clock signal is ‘clk’. Hint: The sequence is 00, 01, 11, 10, 00, 01, 11…
a)

```module twisted_ring_ctr #(parameter WIDTH = 2)
(input logic clk,
input logic reset,
output logic [WIDTH-1:0] q);

always @ (posedge clk) begin
if (reset)
q <= 0;
else begin
q <= q << 1;
q[0] <= ~q[WIDTH-1];
end
end
endmodule```

b)

```module twisted_ring_ctr #(parameter WIDTH = 2)
(input logic clk,
input logic reset,
output logic [WIDTH:0] q);

always @ (posedge clk) begin
if (reset)
q <= 0;
else begin
q <= q << 1;
q[0] <= ~q[WIDTH];
end
end
endmodule```

c)

```module twisted_ring_ctr #(parameter WIDTH = 2)
(input logic clk, input logic reset,
output logic [WIDTH-1:0] q);

always @ (posedge clk) begin
if (reset)
q <= 0;
else begin
q <= q << 1;
q[0] <= q[WIDTH-1];
end
end
endmodule```

d)

```module twisted_ring_ctr #(parameter WIDTH = 2)
(input logic clk, input logic reset,
output logic [WIDTH-1:0] q);

always @ (posedge clk) begin
if (reset)
q <= 0;
else begin
q <= q + 1;
q[0] <= ~q[WIDTH-1];
end
end
endmodule```
Explanation: A Johnson counter is a variation of the ring counter where the complement of the output of the last stage is fed back to the first stage. The above Johnson counter is 2 bits wide, so the width parameter is 2.

7. Write the Verilog code for a 5 bit Johnson counter. The output is ‘q’, active HIGH synchronous reset signal is ‘reset’ and the clock signal is ‘clk’. Hint: The sequence is 00000, 00001, 00011, 00111, 01111, 11111, 11110, 11100, 11000, 10000, 00000, 00001…
a)

```module twisted_ring_ctr #(parameter WIDTH = 5)
(input logic clk,
input logic reset,
output logic [WIDTH-1:0] q);

always @ (posedge clk) begin
if (reset)
q <= 0;
else begin
q <= q << 1;
q[0] <= ~q[WIDTH-1];
end
end
endmodule```

b)

```module twisted_ring_ctr #(parameter WIDTH = 5)
(input logic clk,
input logic reset,
output logic [WIDTH:0] q);

always @ (posedge clk) begin
if (reset)
q <= 0;
else begin
q <= q << 1;
q[0] <= ~q[WIDTH];
end
end
endmodule```

c)

```module twisted_ring_ctr #(parameter WIDTH = 5)
(input logic clk, input logic reset,
output logic [WIDTH-1:0] q);

always @ (posedge clk) begin
if (reset)
q <= 0;
else begin
q <= q << 1;
q[0] <= q[WIDTH-1];
end
end
endmodule```

d)

```module twisted_ring_ctr #(parameter WIDTH = 5)
(input logic clk, input logic reset,
output logic [WIDTH-1:0] q);

always @ (posedge clk) begin
if (reset)
q <= 0;
else begin
q <= q + 1;
q[0] <= ~q[WIDTH-1];
end
end
endmodule```
Explanation: A Johnson counter is a variation of the ring counter where the complement of the output of the last stage is fed back to the first stage. The above Johnson counter is 5 bits wide, so the width parameter is 5.

8. Write the Verilog code for a 4-bit Gray code counter.
a)

```module gray_ctr
#(parameter WIDTH = 4)
(input logic clk,
input logic reset,
output logic [WIDTH-1:0] q);

logic [WIDTH-1:0] counter;

always_ff @ (posedge clk) begin
if (reset) begin
counter <= 0;
end
else begin
counter <= counter + 1;
end
end

always_comb begin
for (int i=1; i < WIDTH; i = i + 1) begin
q[i-1] = counter[i]^counter[i-1];
end
q[WIDTH-1] = counter[WIDTH-1];
end
endmodule```

b)

```module gray_ctr
#(parameter WIDTH = 4)
(input logic clk,
input logic reset,
output logic [WIDTH:0] q);

logic [WIDTH:0] counter;

always_ff @ (posedge clk) begin
if (reset) begin
counter <= 0;
end
else begin
counter <= counter + 1;
end
end

always_comb begin
for (int i=1; i < WIDTH; i = i + 1) begin
q[i-1] = counter[i]^counter[i-1];
end
q[WIDTH-1] = counter[WIDTH-1];
end
endmodule```

c)

```module gray_ctr
#(parameter WIDTH = 4)
(input logic clk,
input logic reset,
output logic [WIDTH:0] q);

logic [WIDTH:0] counter;

always_ff @ (posedge clk) begin
if (reset) begin
counter <= 0;
end
else begin
counter <= counter - 1;
end
end

always_comb begin
for (int i=1; i < WIDTH; i = i + 1) begin
q[i-1] = counter[i]^counter[i-1];
end
q[WIDTH-1] = counter[WIDTH-1];
end
endmodule```

d)

```module gray_ctr
#(parameter WIDTH = 4)
(input logic clk,
input logic reset,
output logic [WIDTH:0] q);

logic [WIDTH:0] counter;

always_ff @ (posedge clk) begin
if (reset) begin
counter <= 0;
end
else begin
counter <= counter << 1;
end
end

always_comb begin
for (int i=1; i < WIDTH; i = i + 1) begin
q[i-1] = counter[i]^counter[i-1];
end
q[WIDTH-1] = counter[WIDTH-1];
end
endmodule```
Explanation: The design is partitioned into 2 parts – one for combinational logic and another for sequential logic. In the sequential logic part, an always_ff block is used. Counter is an internal signal used to store the values and it gets incremented on the positive edge of the clock. Counter is a binary counter, and it has a modulus of 2 raised to the power of its width. In the combinational logic part, an always_comb block is used, where the binary code to gray code conversion is done. This is done by observing two facts:
i) The Most Significant Bit is the same as the Most Significant Bit of the binary counter. This assignment can be done using an assign statement.
ii). For other bits, they are the result of the Ex-Or operation on the corresponding bit of the binary counter and the bit to the immediate right of it. Hence a for loop is suitable to iterate over all the remaining bits and perform the Ex-Or operation over the respective bits of the binary counter. Since a 4-bit Gray code counter is required, the WIDTH parameter is set to 4.

9. Write the Verilog code for a 5-bit gray code counter.
a)

```module gray_ctr
#(parameter WIDTH = 5)
(input logic clk,
input logic reset,
output logic [WIDTH-1:0] q);

logic [WIDTH-1:0] counter;

always_ff @ (posedge clk) begin
if (reset) begin
counter <= 0;
end
else begin
counter <= counter + 1;
end
end

always_comb begin
for (int i=1; i < WIDTH; i = i + 1) begin
q[i-1] = counter[i]^counter[i-1];
end
q[WIDTH-1] = counter[WIDTH-1];
end
endmodule```

b)

```module gray_ctr
#(parameter WIDTH = 5)
(input logic clk,
input logic reset,
output logic [WIDTH:0] q);

logic [WIDTH:0] counter;

always_ff @ (posedge clk) begin
if (reset) begin
counter <= 0;
end
else begin
counter <= counter + 1;
end
end

always_comb begin
for (int i=1; i < WIDTH; i = i + 1) begin
q[i-1] = counter[i]^counter[i-1];
end
q[WIDTH-1] = counter[WIDTH-1];
end
endmodule```

c)

```module gray_ctr
#(parameter WIDTH=5)
(input logic clk,
input logic reset,
output logic [WIDTH:0] q);

logic [WIDTH:0] counter;

always_ff @ (posedge clk) begin
if (reset) begin
counter <= 0;
end
else begin
counter <= counter - 1;
end
end

always_comb begin
for (int i=1; i < WIDTH; i = i + 1) begin
q[i-1] = counter[i]^counter[i-1];
end
q[WIDTH-1] = counter[WIDTH-1];
end
endmodule```

d)

```module gray_ctr
#(parameter WIDTH = 5)
(input logic clk,
input logic reset,
output logic [WIDTH:0] q);

logic [WIDTH:0] counter;

always_ff @ (posedge clk) begin
if (reset) begin
counter <= 0;
end
else begin
counter <= counter << 1;
end
end

always_comb begin
for (int i=1; i < WIDTH; i = i + 1) begin
q[i-1] = counter[i]^counter[i-1];
end
q[WIDTH-1] = counter[WIDTH-1];
end
endmodule```
Explanation: The design is partitioned into 2 parts – one for combinational logic and another for sequential logic. In the sequential logic part, an always_ff block is used. Counter is an internal signal used to store the values and it gets incremented on the positive edge of the clock. Counter is a binary counter, and it has a modulus of 2 raised to the power of its width. In the combinational logic part, an always_comb block is used, where the binary code to gray code conversion is done. This is done by observing two facts:
i) The Most Significant Bit is the same as the Most Significant Bit of the binary counter. This assignment can be done using an assign statement.
ii) For other bits, they are the result of the Ex-Or operation on the corresponding bit of the binary counter and the bit to the immediate right of it. Hence a for loop is suitable to iterate over all the remaining bits and perform the Ex-Or operation over the respective bits of the binary counter. Since a 5-bit Gray code counter is required, the WIDTH parameter is set to 5.

10. Write the Verilog code for a 3-bit gray code counter.
a)

```module gray_ctr
#(parameter WIDTH = 3)
(input logic clk,
input logic reset,
output logic [WIDTH-1:0] q);

logic [WIDTH-1:0] counter;

always_ff @ (posedge clk) begin
if (reset) begin
counter <= 0;
end
else begin
counter <= counter + 1;
end
end

always_comb begin
for (int i=1; i < WIDTH; i = i + 1) begin
q[i-1] = counter[i]^counter[i-1];
end
q[WIDTH-1] = counter[WIDTH-1];
end
endmodule```

b)

```module gray_ctr
#(parameter WIDTH = 3)
(input logic clk,
input logic reset,
output logic [WIDTH:0] q);

logic [WIDTH:0] counter;

always_ff @ (posedge clk) begin
if (reset) begin
counter <= 0;
end
else begin
counter <= counter + 1;
end
end

always_comb begin
for (int i=1; i < WIDTH; i = i + 1) begin
q[i-1] = counter[i]^counter[i-1];
end
q[WIDTH-1] = counter[WIDTH-1];
end
endmodule```

c)

```module gray_ctr
#(parameter WIDTH = 3)
(input logic clk,
input logic reset,
output logic [WIDTH:0] q);

logic [WIDTH:0] counter;

always_ff @ (posedge clk) begin
if (reset) begin
counter <= 0;
end
else begin
counter <= counter - 1;
end
end

always_comb begin
for (int i=1; i < WIDTH; i = i + 1) begin
q[i-1] = counter[i]^counter[i-1];
end
q[WIDTH-1] = counter[WIDTH-1];
end
endmodule```

d)

```module gray_ctr
#(parameter WIDTH = 3)
(input logic clk,
input logic reset,
output logic [WIDTH:0] q);

logic [WIDTH:0] counter;

always_ff @ (posedge clk) begin
if (reset) begin
counter <= 0;
end
else begin
counter <= counter << 1;
end
end

always_comb begin
for (int i=1; i < WIDTH; i = i + 1) begin
q[i-1] = counter[i]^counter[i-1];
end
q[WIDTH-1] = counter[WIDTH-1];
end
endmodule```
Explanation: The design is partitioned into 2 parts – one for combinational logic and another for sequential logic. In the sequential logic part, an always_ff block is used. Counter is an internal signal used to store the values and it gets incremented on the positive edge of the clock. Counter is a binary counter, and it has a modulus of 2 raised to the power of its width. In the combinational logic part, an always_comb block is used, where the binary code to gray code conversion is done. This is done by observing two facts:
i) The Most Significant Bit is the same as the Most Significant Bit of the binary counter. This assignment can be done using an assign statement.
ii) For other bits, they are the result of the Ex-Or operation on the corresponding bit of the binary counter and the bit to the immediate right of it. Hence a for loop is suitable to iterate over all the remaining bits and perform the Ex-Or operation over the respective bits of the binary counter. Since a 3-bit Gray code counter is required, the WIDTH parameter is set to 3.

11. Write the Verilog code for an 8-bit gray code counter.
a)

```module gray_ctr
#(parameter WIDTH = 8)
(input logic clk,
input logic reset,
output logic [WIDTH-1:0] q);

logic [WIDTH-1:0] counter;

always_ff @ (posedge clk) begin
if (reset) begin
counter <= 0;
end
else begin
counter <= counter + 1;
end
end

always_comb begin
for (int i=1; i < WIDTH; i = i + 1) begin
q[i-1] = counter[i]^counter[i-1];
end
q[WIDTH-1] = counter[WIDTH-1];
end
endmodule```

b)

```module gray_ctr
#(parameter WIDTH = 8)
(input logic clk,
input logic reset,
output logic [WIDTH:0] q);

logic [WIDTH:0] counter;

always_ff @ (posedge clk) begin
if (reset) begin
counter <= 0;
end
else begin
counter <= counter + 1;
end
end

always_comb begin
for (int i=1; i < WIDTH; i = i + 1) begin
q[i-1] = counter[i]^counter[i-1];
end
q[WIDTH-1] = counter[WIDTH-1];
end
endmodule```

c)

```module gray_ctr
#(parameter WIDTH = 8)
(input logic clk,
input logic reset,
output logic [WIDTH:0] q);

logic [WIDTH:0] counter;

always_ff @ (posedge clk) begin
if (reset) begin
counter <= 0;
end
else begin
counter <= counter - 1;
end
end

always_comb begin
for (int i=1; i < WIDTH; i = i + 1) begin
q[i-1] = counter[i]^counter[i-1];
end
q[WIDTH-1] = counter[WIDTH-1];
end
endmodule```

d)

```module gray_ctr
#(parameter WIDTH = 8)
(input logic clk,
input logic reset,
output logic [WIDTH:0] q);

logic [WIDTH:0] counter;

always_ff @ (posedge clk) begin
if (reset) begin
counter <= 0;
end
else begin
counter <= counter << 1;
end
end

always_comb begin
for (int i=1; i < WIDTH; i = i + 1) begin
q[i-1] = counter[i]^counter[i-1];
end
q[WIDTH-1] = counter[WIDTH-1];
end
endmodule```
Explanation: The design is partitioned into 2 parts – one for combinational logic and another for sequential logic. In the sequential logic part, an always_ff block is used. Counter is an internal signal used to store the values and it gets incremented on the positive edge of the clock. Counter is a binary counter, and it has a modulus of 2 raised to the power of its width. In the combinational logic part, an always_comb block is used, where the binary code to gray code conversion is done. This is done by observing two facts:
i. The Most Significant Bit is the same as the Most Significant Bit of the binary counter. This assignment can be done using an assign statement.
ii. For other bits, they are the result of the Ex-Or operation on the corresponding bit of the binary counter and the bit to the immediate right of it. Hence a for loop is suitable to iterate over all the remaining bits and perform the Ex-Or operation over the respective bits of the binary counter. Since an 8-bit Gray code counter is required, the WIDTH parameter is set to 8.

12. The sequences produced by a 2-bit Gray code counter and a 2-bit Johnson code counter are identical.
a) True
b) False

Explanation. A 2-bit Gray code counter and a 2-bit Johnson counter have identical sequences. Hence the answer is true. This can be checked by comparing the sequences of 2-bit Johnson and 2-bit Gray counters.

13. The sequences produced by a 3-bit Gray code counter and a 3-bit Johnson code counter are identical.
a) True
b) False

Explanation. A 2-bit Gray code counter and a 2-bit Johnson counter have different sequences. Hence the answer is False. This can be checked by comparing the sequences of 2-bit Johnson and 2-bit Gray counters.

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