This set of Sequential Logic Design Multiple Choice Questions & Answers (MCQs) focuses on “Synthesis of VHDL Code”.
1. What does VHDL stand for?
a) Very High Definition Language
b) Virtual High Definition Language
c) Very High Speed Integrated Circuit Hardware Description Language
d) Virtual Hardware Description Language
View Answer
Explanation: VHDL stands for Very High Speed Integrated Circuit Hardware Definition Language. It is used in electronic circuit design automation to describe digital and mixed signal systems such as FPGA and ICs. VHDL is also useful for virtual logic design.
2. Which one of the following is used to define input and output ports in a VHDL code?
a) Entity
b) Architecture
c) Generic
d) End
View Answer
Explanation: VHDL stands for Very High Speed Integrated Circuit Hardware Definition Language. It is used in electronic circuit design automation to describe digital and mixed signal systems such as FPGA and ICs. Entity is a keyword used in VHDL to define or specify i/o ports.
3. Which one of the following is used to define a input port in VHDL?
a) Ip
b) Input
c) In
d) In_bit
View Answer
Explanation: VHDL stands for Very High Speed Integrated Circuit Hardware Definition Language. It is used in electronic circuit design automation to describe digital and mixed signal systems such as FPGA and ICs. VHDL codes define a whole digital model. Describing ports is a part of it. The “In” keyword is used in VHDL to define input ports.
4. Which of the following is applicable for data flow modelling of VHDL?
a) The flow of data through the entity is expressed using concurrent (parallel) signal
b) The behaviour of an entity as set of statements is executed sequentially in the specified order
c) An entity is described as a set of interconnected components
d) Architecture body is composed of two parts − the declarative part (before the keyword begin) and the statement part (after the keyword begin)
View Answer
Explanation: VHDL stands for very high-speed integrated circuit hardware description language. It is a programming language used to model a digital system by dataflow, behavioural and structural style of modelling. In dataflow modelling the flow of data through the entity is expressed using concurrent (parallel) signal.
5. Which of the following is applicable for behavioural modelling of VHDL?
a) The flow of data through the entity is expressed using concurrent (parallel) signal
b) The behaviour of an entity as set of statements is executed sequentially in the specified order
c) An entity is described as a set of interconnected components
d) Architecture body is composed of two parts − the declarative part (before the keyword begin) and the statement part (after the keyword begin)
View Answer
Explanation: VHDL stands for very high-speed integrated circuit hardware description language. It is a programming language used to model a digital system by dataflow, behavioural and structural style of modelling. In behavioural modelling the behaviour of an entity as set of statements is executed sequentially in the specified order.
6. Which of the following is applicable for structural modelling of VHDL?
a) The flow of data through the entity is expressed using concurrent (parallel) signal
b) The behaviour of an entity as set of statements is executed sequentially in the specified order
c) An entity is described as a set of interconnected components
d) Architecture body is composed of two parts − the declarative part (before the keyword begin) and the statement part (after the keyword begin)
View Answer
Explanation: VHDL stands for very high-speed integrated circuit hardware description language. It is a programming language used to model a digital system by dataflow, behavioural and structural style of modelling. In structural modelling An entity is described as a set of interconnected components.
7. Which of the following is a VHDL library?
a) stdio
b) conio
c) ieee
d) pillow
View Answer
Explanation: VHDL libraries allow you to store commonly used packages and entities that you can use in your VHDL files. “stdio” and “conio” are C library files. “pillow” is a python library. So “ieee” is a standard library file used with VHDL.
8. Which among the following is pre-defined in the standard package as one-dimensional array type comprising each element of BIT type?
a) Bit_vector
b) Bit
c) Boolean
d) Bool
View Answer
Explanation: VHDL libraries allow you to store commonly used packages and entities that you can use in your VHDL files. Bit_vector is pre-defined in the standard package as one-dimensional array type comprising each element of BIT type.
9. What are the possible values of the BIT data type?
a) o to 9
b) 0, 1
c) 1 to 9
d) 0, 1, 2
View Answer
Explanation: Data types are used in VHDL to define variables of a specific types. There are several data types used in VHDL. BIT is one of them that is used to represents bits. So this can represent 2 values 0 and 1.
10. What are the possible values of the STD_LOGIC data type?
a) o to 9
b) 0, 1
c) X, 0, 1, Z
d) 0, 1, 2
View Answer
Explanation: Data types are used in VHDL to define variables of a specific types. The STD_LOGIC data type can have 4 values – X, 0, 1 and Z. It can have other values also but they are not synthesizable – i.e. they cannot be implemented on CPLDs and FPGAs.
11. Which one of the following code is used to end an if block?
a) else
b) end
c) end if
d) stop
View Answer
Explanation: VHDL stands for very high-speed integrated circuit hardware description language. It is a programming language used to model a digital system by dataflow, behavioural and structural style of modelling. For every if statement mentioned inside code, there must be an end if statement to signify the end of if block.
12. Which one of the following is a basic building block of VHDL?
a) Entity
b) Architecture
c) Port
d) Variable
View Answer
Explanation: VHDL stands for very high-speed integrated circuit hardware description language. It is a programming language used to model a digital system by dataflow, behavioural and structural style of modelling. Entity is a basic building block of VHDL.
13. What is the type of bus in VHDL?
a) Vector
b) Signal
c) Entity
d) Bit_Vector
View Answer
Explanation: VHDL stands for very high-speed integrated circuit hardware description language. It is a programming language used to model a digital system by dataflow, behavioural and structural style of modelling. Bus is also a specific signal that may have drivers turned off.
14. What is the equivalent design of the following VHDL code?
Signal count: integer range 0 to 7
a) A shift register of 3-bit size
b) A master slave flip-flop
c) A 3-bit counter
d) A 3-bit PIPO register
View Answer
Explanation: A signal is assigned a new value in VHDL with what is known as a “signal assignment statement”, as we have seen in the examples of the half adder and full adder. An assignment to a signal defines a driver on that signal. Here we see that we can represent numbers from 0 to seven as groups of 3 bits. So the code defines a signal variable that is a 3-bit counter.
15. If one wants to perform no action, in any true condition, then which of the following keyword can be used?
a) NULL
b) NOP
c) NO Operation
d) Next
View Answer
Explanation: A NULL statement is generally used in CASE statement. The system will ignore the null statement and proceed to the next statement. This statement is used to explicitly state that no action is to be performed when a condition is true. Generally, this can be used in the OTHERS part of the CASE block.
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