# Digital Circuits Questions and Answers – Up Down Counter

This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Up Down Counter”.

1. UP-DOWN counter is a combination of ____________
a) Latches
b) Flip-flops
c) UP counter
d) Up counter & down counter

Explanation: As the name suggests UP-DOWN, it means that it has up-counter and down-counter as well. It alternatively counts up and down.

2. UP-DOWN counter is also known as ___________
a) Dual counter
b) Multi counter
c) Multimode counter
d) Two Counter

Explanation: UP-DOWN counter is also known as multimode counter because it has capability of counting upward as well as downwards.

3. In an UP-counter, each flip-flop is triggered by ___________
a) The output of the next flip-flop
b) The normal output of the preceding flip-flop
c) The clock pulse of the previous flip-flop
d) The inverted output of the preceding flip-flop

Explanation: In an UP-counter, each flip-flop is triggered by the normal output of the preceding flip-flop. UP-counter counts from 0 to a maximum value.

4. In DOWN-counter, each flip-flop is triggered by ___________
a) The output of the next flip-flop
b) The normal output of the preceding flip-flop
c) The clock pulse of the previous flip-flop
d) The inverted output of the preceding flip-flop

Explanation: In DOWN-counter, each flip-flop is triggered by the inverted output of the preceding flip-flop. DOWN-counter counts from a maximum value to 0.

5. Binary counter that count incrementally and decrement is called ___________
a) Up-down counter
b) LSI counters
c) Down counter
d) Up counter

Explanation: Binary counter that counts incrementally and decrement is called UP-DOWN counter/multimode counter. It alternately counts up and down.

6. Once an up-/down-counter begins its count sequence, it ___________
a) Starts counting
b) Can be reversed
c) Can’t be reversed
d) Can be altered

Explanation: In up/down ripple counter once the counting begins, we can simply change the pulse M (mode control) M = 0 or 1 respectively for UP counter or Down counter.

7. In 4-bit up-down counter, how many flip-flops are required?
a) 2
b) 3
c) 4
d) 5

Explanation: An n-bit bit counter requires n number of FFs. In a 4-bit up-down counter, there are 4 J-K flip-flops required.

8. A modulus-10 counter must have ________
a) 10 flip-flops
b) 4 Flip-flops
c) 2 flip-flops
d) Synchronous clocking

Explanation: 2n-1 < = N < = 2n
For modulus-10 counter, N = 10. Therefore, 23 < = 10 < = 24. Thus, n = 4, and therefore, we require 4 FFs.

9. Which is not an example of a truncated modulus?
a) 8
b) 9
c) 11
d) 15

Explanation: An n-bit counter whose modulus is less than the maximum possible is called a truncated counter. Here, 9, 11 and 15 modulus counters are truncated counters. Whereas, modulus-8 is not a truncated counter.

10. The designation means that the ________
a) Up count is active-HIGH, the down count is active-LOW
b) Up count is active-LOW, the down count is active-HIGH
c) Up and down counts are both active-LOW
d) Up and down counts are both active-HIGH

Explanation: The designation means that the up count is active-HIGH, the down count is active-LOW. Active-High means that up-count would be triggered when clock is 1 else when clock is 0, down-count would be triggered, which is referred to as Active-low.

11. An asynchronous binary up counter, made from a series of leading edge-triggered flip-flops, can be changed to a down counter by ________
a) Taking the output on the other side of the flip-flops (instead of Q)
b) Clocking of each succeeding flip-flop from the other side (instead of Q)
c) Changing the flip-flops to trailing edge triggering
d) All of the Mentioned

Explanation: By all of the mentioned ideas, an asynchronous binary up counter, made from a series of leading edge-triggered flip-flops, can be changed to a down counter. Edge-triggered FFs refer to FFs being triggered during a clock transition from LOW to HIGH or HIGH to LOW.

12. A 4-bit binary up counter has an input clock frequency of 20 kHz. The frequency of the most significant bit is ________
a) 1.25 kHz
b) 2.50 kHz
c) 160 kHz
d) 320 kHz

Explanation: Input clock is given by 20/2 kHz. So, count on the basis of 10 kHz clock. And MSB changes on 8th stage; Hence, f = 10/8 = 1.25 kHz.

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