Digital Circuits Questions and Answers – Flip Flops – 3

This set of Digital Electronic/Circuits question bank focuses on “Flip Flops – 3”.

1. Which circuit is generated from D flip-flop due to addition of an inverter by causing reduction in the number of inputs?
a) Gated JK-latch
b) Gated SR-latch
c) Gated T-latch
d) Gated D-latch

Explanation: Since, both inputs of the D flip-flop are connected through an inverter. And this causes reduction in the number of inputs.

2. The characteristic of J-K flip-flop is similar to _____________
a) S-R flip-flop
b) D flip-flop
c) T flip-flop
d) Gated T flip-flop

Explanation: In an S-R flip-flop, S refers to “SET” whereas R refers to “RESET”. The same behaviour is shown by J-K flip-flop.

3. A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting ___________
a) Two AND gates
b) Two NAND gates
c) Two NOT gates
d) Two OR gates

Explanation: A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting two AND gates.

4. How is a J-K flip-flop made to toggle?
a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1

Explanation: When j=k=1 then the race condition is occurs that means both output wants to be HIGH. Hence, there is toggle condition is occurs, where 0 becomes 1 and 1 becomes 0. That is device is either set or reset.

5. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ___________
a) Parity error checking
b) Ones catching
c) Digital discrimination
d) Digital filtering

Explanation: Ones catching means that the input transitioned to a 1 and back very briefly (unintentionally due to a glitch), but the flip-flop responded and latched it in anyway, i.e., it caught the 1. Similarly for 0’s catching.

6. In J-K flip-flop, “no change” condition appears when ___________
a) J = 1, K = 1
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 0, K = 0

Explanation: If J = 0, K = 0, the output remains unchanged. This is the memory storing state.

7. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________
a) Constantly LOW
b) Constantly HIGH
c) A 20 kHz square wave
d) A 10 kHz square wave

Explanation: The flip flop is sensitive only to the positive or negative edge of the clock pulse. So, the flip-flop toggles whenever the clock is falling/rising at edge. This triggering of flip-flop during the transition state, is known as Edge-triggered flip-flop. Thus, the output curve has a time period twice that of the clock. Frequency is inversely related to time period and hence frequency gets halved.

8. What is the significance of the J and K terminals on the J-K flip-flop?
a) There is no known significance in their designations
b) The J represents “jump,” which is how the Q output reacts whenever the clock goes high and the J input is also HIGH
c) The letters were chosen in honour of Jack Kilby, the inventory of the integrated circuit
d) All of the other letters of the alphabet are already in use

Explanation: The letters J & K were chosen in honour of Jack Kilby, the inventory of the integrated circuit. In J&K flip-flops, the invalid state problem is resolved, thus leading to the toggling of states.

9. On a J-K flip-flop, when is the flip-flop in a hold condition?
a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1

Explanation: At J=0 k=0 output continues to be in the same state. This is the memory storing state.

10. Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________
a) 00
b) 11
c) 01
d) 10

Explanation: Every O/P repeats after its mod. Here mod is 4 (because 2 flip-flops are used. So mod = 22 = 4). So after 4 clock pulses the O/P repeats i.e. 00.

11. Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________
a) 1 kHz
b) 2 kHz
c) 4 kHz
d) 16 kHz

Explanation: 32/2=16:-first flip-flop, 16/2=8:- second flip-flop, 8/2=4:- third flip-flop, 4/2=2:- fourth flip-flop. Since the output frequency is determined on basis of the 4th flip-flop.

12. Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.
a) 10.24 kHz
b) 5 kHz
c) 30.24 kHz
d) 15 kHz

Explanation: 12 flip flops = 212 = 4096
Input Clock frequency = 20.48*106 = 20480000
Output Clock frequency = 20480000/4096 = 5000 i.e., 5 kHz.

13. How many flip-flops are in the 7475 IC?
a) 2
b) 1
c) 4
d) 8

Explanation: There are 4 flip-flops used in 7475 IC and those are D flip-flops only.

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