# Embedded Systems Questions and Answers – DRAM Refreshing Techniques

This set of Embedded Systems Questions and Answers for Aptitude test focuses on “DRAM Refreshing Techniques”.

1. Which is the very basic technique of refreshing DRAM?
a) refresh cycle
b) burst refresh
c) distributive refresh
d) software refresh

Explanation: The DRAM needs to be periodically refreshed and the very basic technique is a special refresh cycle, during these cycles no other access is permitted. The whole chip is refreshed within a particular time period otherwise, the data will be lost.

2. How is the refresh rate calculated?
a) by refresh time
b) by the refresh cycle
c) by refresh cycle and refresh time
d) refresh frequency and refresh cycle

Explanation: The time required for refreshing the whole chip is known as refresh time. The number of access needed to complete refresh is called as the number of cycles. The number of cycles divided by the refresh time gives the refresh rate.

3. Which is the commonly used refresh rate?
a) 125 microseconds
b) 120 microseconds
c) 130 microseconds
d) 135 microseconds

Explanation: There are two refresh rates used in common. They are standard refresh rate of 15.6 microseconds and 125 microseconds which the extended form.

4. How can we calculate the length of the refresh cycle?
a) twice of normal access
b) thrice of normal access
c) five times of normal access
d) six times of normal access

Explanation: Each of the refresh cycles is approximately as twice as the length of the normal access, for example, a 70ns DRAM has a refresh cycle time of 130ns.

5. What type of error occurs in the refresh cycle of the DRAM?
a) errors in data
b) power loss
c) timing issues
d) not accessing data

Explanation: When the refresh cycle in a DRAM is running, it will not access data, so the processor will have to wait for its data. This arises some timing issues.
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6. What is the worst case delay of the burst refresh in 4M by 1 DRAM?
a) 0.4ms
b) 0.2ms
c) 170ns
d) 180ns

Explanation: A 4M by 1 DRAM have 1024 refresh cycles. Bursting delay will be 0.2ms that are, the worst case delay is 1024 times larger than that of the single refresh cycle. The distributed delay is about 170ns.

7. Which refresh techniques depends on the size of time critical code for calculating the refresh cycle?
a) burst refresh
b) distributed refresh
c) refresh cycle
d) software refresh

Explanation: Most of the system uses the distributed method and depending on the size of the time critical code, the number of refresh cycles can be calculated.

8. Which of the following uses a timer for refresh technique?
a) RAS
b) CBR
c) software refresh
d) CAS

Explanation: The software refresh performs the action by using a routine to periodically cycle through the memory and refreshes. It uses a timer in the program generating an interrupt. This interrupt performs the refreshing part in the DRAM.

9. What is the main disadvantage in the software refresh of the DRAM?
a) timer
b) delay
c) programming delay
d) debugging

Explanation: Debugging in software refresh is very difficult to perform because they may stop the refreshing and if the refreshing is stopped, the contents get lost.

10. Which refresh technique is useful for low power consumption?
a) Software refresh
b) CBR
c) RAS
d) Burst refresh

Explanation: CBR that is, CAS before RAS refresh is the one which is commonly used. It has low power consumption quality because it does not have address bus and the buffers can be switched off. It is worked by using an internal address counter which is stored on the memory chip itself and this can be incremented periodically.

11. Which refreshing techniques generate a recycled address?
a) RAS
b) CBR
c) Distributed refresh
d) Software refresh

Explanation: The row address is placed on the address bus and the column address is held off which generates the recycle address. The address generation is done by an external hardware controller.

12. Which of the following uses a software refresh in the DRAM?
a) 8086
b) 80386
c) Pentium
d) Apple II personal computer

Explanation: The Apple II personal computer has a particular memory configuration, periodically the DRAM gets blocked and is used for video memory accessing to update the screen which can refresh the DRAM.

13. How do CBR works?
a) by asserting CAS before RAS
b) by asserting CAS after RAS
c) by asserting RAS before CAS
d) by asserting CAS only

Explanation: CBR works by an internal address counter which is periodically incremented. The mechanism is based on CAS before RAS. Each time when RAS is asserted, the refresh cycle performs and the counter is incremented.

14. Which of the refresh circuit is similar to CBR?
a) software refresh
b) hidden refresh
c) burst refresh
d) distribute refresh

Explanation: In the hidden refresh, the refresh cycle is added to the end of a normal read cycle. The RAS signal goes high and is then asserted low. At the end of the read cycle, the CAS is still asserted. This is similar to the CBR mechanism, that is, toggling of the RAS signal at the end of the read cycle starts a CBR refresh cycle.

15. Which technology is standardized in DRAM for determining the maximum time interval between the refresh cycle?
a) IEEE
b) RAPID
c) JEDEC
d) UNESCO

Explanation: The maximum time interval between refresh cycle is standardized by JEDEC, Joint Electron Device Engineering Council which is an independent semiconductor engineering trade organization. This standardized JEDEC in DRAM is specified in the manufacturer’s chip specification.

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