This set of Embedded Systems Multiple Choice Questions & Answers (MCQs) focuses on “Burst Interfaces”.
1. Which of the following include special address generation and data latches?
a) burst interface
b) peripheral interface
d) input-output interfacing
Explanation: The burst interfacing has special memory interfaces which include special address generation and data latches that help in the high performance of the processors. It takes the advantages of both the nibble mode memories and paging.
2. Which of the following makes use of the burst fill technique?
a) burst interfaces
c) peripheral interfaces
d) input-output interfaces
Explanation: The burst interfaces use the burst fill technique in which the processor will access four words in succession, which fetches the complete cache line or written out to the memory.
3. How did burst interfaces access faster memory?
c) static column memory
Explanation: The speed of the memory can be improved by the page mode or the static column memory which offer a faster access in a single cycle.
4. Which of the following memory access can reduce the clock cycles?
a) bus interfacing
b) burst interfacing
Explanation: The burst interfaces reduces the clock cycles. For fetching four words with a three clock memory, it will take 12 clock cycle but in the burst interface, it will only take five clocks to access the data.
5. How many clocks are required for the first access in the burst interface?
Explanation: In the burst interface, the first access of the memory address requires two clock cycles and a single cycle for the remaining memory address.
6. In which of the following access, the address is supplied?
a) the first access
b) the second access
c) third access
d) fourth access
Explanation: In the burst interface, the address is supplied only for the first access and not for the remaining accesses. An external logic is required for the additional addresses for the memory interface.
7. What type of timing is required for the burst interfaces?
Explanation: The burst interfacing uses an unequal timing. It takes two clocks for the first access and only one for the remaining accesses which make it an unequal timing.
8. How can gate delays be reduced?
a) synchronous memory
b) asynchronous memory
c) pseudo asynchronous memory
d) symmetrical memory
Explanation: The burst interfaced is associated with the SRAM and for the efficiency of the SRAM, it uses a synchronous memory on-chip latches to reduce the gate delays.
9. In which memory does the burst interfaces act as a part of the cache?
d) Flash memory
Explanation: The burst interface is associated with the static RAM.
10. Which of the following uses a wrap around burst interfacing?
d) US 5729504 A
Explanation: MC68040 is developed by the Motorola which uses a wrap around burst interfacing. MC68030 is also developed by Motorola but it uses a linear line fill burst. HyperBus can switch to both linear and wrap around burst. US 5729504 A uses a linear burst fill.
11. Which of the following is a Motorola’s protocol product?
c) Slave interfaces
d) AXI slave interfaces
Explanation: MCM62940 protocol is developed by Motorola, whereas Slave interfaces, AXI slave interfaces are for ARM. Avalon is developed by Altera.
12. Which of the following uses a linear line fill interfacing?
c) US 74707 B2
d) Hyper Bus
Explanation: MC68030 uses a linear burst fill whereas MC68040, US 74707 B2 uses to wrap around burst interfacing. HyperBus can switch to both linear and wrap around interfacing.
13. Which of the following protocol matches the Intel 80486?
c) US 74707 B2
d) Hyper Bus
Explanation: The MCM62486 has an on-chip counter that matches the Intel 80486 and is developed by the Motorola.
14. Which of the following protocol matches the MC68040?
b) US 5729504 A
Explanation: The MCM62940 and MCM62486 are the specific protocols developed by Motorola, in which the MCM62940 has an on-chip counter which matches the wrap-around burst interfacing of the MC68040.
Sanfoundry Global Education & Learning Series – Embedded System.
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