This set of Embedded Systems Multiple Choice Questions & Answers (MCQs) focuses on “The Berkeley RISC Model and Digital Signal Processing”.
1. How many bit register set does RISC 1 model used?
Explanation: RISC 1 model is developed in the 1970s and uses a large register set of 138*32 bit. These are arranged in eight overlapping windows which have 24 registers each and these windows are split so that six registers can be used during function calls.
2. Which of the following processor commercializes the Berkeley RISC model?
Explanation: The Berkeley RISC design was developed between the year 1980 and 1984 and later on the RISC design were commercialized as SPARC processor.
3. How many transistors does RISC 1 possess?
Explanation: The final design of RISC concept is called the RISC 1 which was published by ACM ISCA. It possesses 44500 transistors which can implement 31 instruction.
4. How many registers does RISC 1 model have?
Explanation: The RISC 1 model have 78 registers of size 32 bits.
5. Which of the architectures are made to speed up the processor?
c) program stored
d) von Neumann
Explanation: RISC architecture is made for speeding up the processor with limited execution time whereas CISC architecture is mainly for code efficiency.
6. How did 8086 pass its control to 8087?
a) BUSY instruction
b) ESCAPE instruction
c) CONTROL instruction
d) fetch 8087
Explanation: When 8086 comes across any floating point arithmetic operations, it executes ESCAPE instruction code in order to pass the control of bus and instruction op-code to 8087.
7. Which of the following processor supports MMX instructions?
c) Intel Pentium
Explanation: MMX instructions or multimedia extensions were introduced in Pentium processors to provide support for multimedia software running on a PC.
8. Which of the following processors has a speculative execution?
c) Intel Pentium
d) Pentium pro
Explanation: Speculative execution is executed speculatively that is, following the predicted branch paths in the code until the true path is determined. If the processor executes correctly, then the performance is gained, if not, the results are discarded and the processor continues to execute until the correct path is identified.
9. How many bit accumulator does DSP56000 have?
Explanation: The ALU of DSP56000 have two 56-bit accumulator A and B each of which have small register with it.
10. How many additional registers does DSP56000 have?
Explanation: In addition to the six registers of DSP56000, it has four 24-bit registers X1,X0,Y1,Y0 which can be concatenated to form 48 bit register X and Y.
11. What does MAC instruction of DSP56000 stand for?
a) multiply accumulator
b) multiple access
c) multiple accounting
d) multiply accumulator counter
Explanation: When MAC instruction is executed, the two of the 24-bit additional registers are multiplied together and then added or subtracted from A and B. It takes place in a single machine cycle of 75ns at 27MHz.
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