This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Introduction to hardware description language”.
1. The full form of HDL is _________________
a) Higher Descriptive Language
b) Higher Definition Language
c) Hardware Description Language
d) High Descriptive Language
Explanation: The full form of HDL is Hardware Description Language.
2. The full form of VHDL is _____________
a) Very High Descriptive Language
b) Verilog Hardware Description Language
c) Variable Definition Language
d) None of the Mentioned
Explanation: The full form of VHDL is Verilog Hardware Description Language.
3. VHSIC stands for _____________
a) Very High Speed Integrated Circuits
b) Very Higher Speed Integration Circuits
c) Variable High Speed Integrated Circuits
d) Variable Higher Speed Integration Circuits
Explanation: VHSIC stands for Very High Speed Integrated Circuits.
4. VHDL is being used for _____________
c) Synthesis of large digital design
d) All of the Mentioned
Explanation: The full form of VHDL is Verilog Hardware Description Language. The acronym of VHDL itself captures the entire theme of the language and it describes the hardware in the same manner as does the schematic. So, it is used as documentation, verification and synthesis of large digital designs.
5. The use of VHDL can be done in _____ ways.
Explanation: The VHDL has three coding styles are: (i) data flow, (ii) structural, (iii) behavioural.
6. At high frequencies when the sampling interval is too long in a frequency counter _____________
a) The counter works fine
b) The counter undercounts the frequency
c) The measurement is less precise
d) The counter overflows
Explanation: Let the sampling time be 1 sec. This means the counter will count the number of pulses from the unknown signal for 1sec duration and would display it after 1 sec. thus if the signal is of 800 Hz, at the end of 1 sec, counter would have counted up to 800. Thus, in case of high frequencies and high sampling time, counter might count beyond its limit and overflows.
7. The output frequency related to the sampling interval of a frequency counter as _____________
a) Directly with the sampling interval
b) Inversely with the sampling interval
c) More precision with longer sampling interval
d) Less precision with longer sampling interval
Explanation: Sampling interval means a particular frequency range in which the device operates correctly. Thus, more precision is produced with longer sampling interval.
8. In an HDL application of a stepper motor, what is done next after an up/down counter is built?
a) Build the sequencer
b) Test it on a simulator
c) Test the decoder
d) Design an intermediate integer variable
Explanation: Simulator is a software which is used in the testing of the stepper motor using up/down counter.
9. In a digital clock application, the basic frequency must be divided down as _____________
a) 1 Hz
b) 60 Hz
c) 100 Hz
d) 1000 Hz
Explanation: Minimum count is 1 sec and time = 1/freq. So, t = 1/1 = 1Hz.
10. What does the data signal do in the keypad application?
a) The row and column encoded data
b) The ring encoded data
c) The freeze locator data
d) The ring counter data
Explanation: The data signal arrange the information with the help of data flow in row and column manner. It encodes the data to be sent.
11. When a key is pressed, what does the ring counter in the HDL keypad application do?
a) Count to find the row
c) Count to find the column
d) Start the D flip-flop
Explanation: The data signal arrange the information with the help of data flow in row and column manner. It encodes the data to be sent. When a key is pressed the ring counter in the HDL scans the information provided by the user and counts to find the row.
12. A step which should be followed in project management is known as _____________
a) Overall definition
b) System documentation
c) Synthesis and testing
d) System integration
Explanation: System documentation is the second step of project management in which a result of the system is noted simultaneously.
13. In the keypad application, the preset state of the ring counter define _____________
a) The NANDing of the columns
b) The NANDing of the rows
c) The proper output of the column encoder
d) The proper output of the row encoder
Explanation: When a key is pressed the ring counter in the HDL scans the information provided by the user and counts to find the row. The preset state of the ring counter define the proper output of the row encoder.
14. A major block which is not a part of an HDL frequency counter _____________
a) Timing and control unit
c) Display register
d) Bit shifter
Explanation: Bit shifter is part of a register in which bit shifting takes place bit-by-bit either left or right.
15. A stepper motor HDL application must include _____________
a) Sequencers and multiplexers
b) Types and bits
c) Counters and decoders
d) Variables and processes
Explanation: A stepper motor (also referred to as step or stepping motor) is an electromechanical device achieving mechanical movements through the conversion of electrical pulses. A stepper motor HDL application must include counters and decoders for position control. It is tested on the simulator.
Sanfoundry Global Education & Learning Series – Digital Circuits.
To practice all areas of Digital Circuits, here is complete set of 1000+ Multiple Choice Questions and Answers.