This set of Digital Electronic/Circuits Test focuses on “4-Bit Parallel Adder/Subtractor – 2”.
1. For a 4-bit parallel adder, if the carry-in is connected to a logical HIGH, the result is:
a) The same as if the carry-in is tied LOW since the least significant carry-in is ignored
b) That carry-out will always be HIGH
c) A one will be added to the final result
d) The carry-out is ignored
Explanation: For a 4-bit parallel adder, if the carry-in is connected to a logical HIGH, one will be added to the final result as a result because carry-in gives output as 1.
2. Fast-look-ahead carry circuits found in most 4-bit full-adder circuits which
a) Determine sign and magnitude
b) Reduce propagation delay
c) Add a 1 to complemented inputs
d) Increase ripple delay
Explanation: A carry-lookahead adder (CLA) is a type of adder used in digital logic. A carry-lookahead adder improves speed by reducing the amount of time required to determine carry bits.
3. One way to make a four-bit adder to perform subtraction is by:
a) Inverting the output
b) Inverting the carry-in
c) Inverting the B inputs
d) Grounding the B inputs
Explanation: Since, a four bit adder has four A, four B and a carry at the input end. So, for subtraction to be performed, all the Bs terminal should be inverted.
4. What distinguishes the look-ahead-carry adder?
a) It is slower than the ripple-carry adder
b) It is easier to implement logically than a full adder
c) It is faster than a ripple-carry adder
d) It requires advance knowledge of the final answer
Explanation: It is slower than the ripple-carry adder. It is easier to implement logically than a full adder. It is faster than a ripple-carry adder.
5. Carry lookahead logic uses the concepts of
a) Inverting the inputs
b) Complementing the outputs
c) Generating and propagating carries
d) Ripple factor
Explanation: Carry lookahead logic uses the concepts of generating and propagating carries. Although in the context of a carry lookahead adder, it is most natural to think of generating and propagating in the context of binary addition, the concepts can be used more generally than this.
6. What is one disadvantage of the ripple-carry adder?
a) The interconnections are more complex
b) More stages are required to a full adder
c) It is slow due to propagation time
d) All of the Mentioned
Explanation: The main disadvantage in using this type of adders is that the time delay increases as for each adder to add the carry should be generated in the previous adder, and for that to add the carry from the one before is required.
7. The carry propagation delay in 4-bit full-adder circuits:
a) Is cumulative for each stage and limits the speed at which arithmetic operations are performed
b) Is normally not a consideration because the delays are usually in the nanosecond range
c) Decreases in direct ratio to the total number of full-adder stages
d) Increases in direct ratio to the total number of full-adder stages, but is not a factor in limiting the speed of arithmetic operations
Explanation: The carry propagation delay in 4-bit full-adder circuits is cumulative for each stage and limits the speed at which arithmetic operations are performed.
8. What is Manchester carry chain?
a) Is a chain of controlled inverter
b) Variation of a carry-lookahead adder
c) Variation of a full-adder
d) None of the Mentioned
Explanation: The Manchester carry chain is a variation of the carry-lookahead adder that uses shared logic to lower the transistor count.
9. The main disadvantage of Manchester carry chain is
a) Ripple factor
b) Propagation delay
c) Capacitive load
d) Both propagation delay and capacitive load
Explanation: One of the major downsides of the Manchester carry chain is that the capacitive load of all of these outputs, together with the resistance of the transistors causes the propagation delay to increase much more quickly than a regular carry lookahead.
10. The summing outputs of a half or full-adder are designated by which Greek symbol?
Explanation: The summing outputs of a half or full-adder are designated by “sigma” which is a Greek symbol.
11. Why is a fast-look-ahead carry circuit used in the 7483 4-bit full-adder?
a) To decrease the cost
b) To make it smaller
c) To slow down the circuit
d) To speed up the circuit
Explanation: Since, it is easy to implement and can be implemented on any types of chip and have capability to reduce propagation delay, which helps in increasing the speed of 7483 4-bit full-adder.
Sanfoundry Global Education & Learning Series – Digital Circuits.
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