This set of Digital Electronic/Circuits Test focuses on “4-Bit Parallel Adder/Subtractor”.

1. For a 4-bit parallel adder, if the carry-in is connected to a logical HIGH, the result is ___________
a) The same as if the carry-in is tied LOW since the least significant carry-in is ignored
b) That carry-out will always be HIGH
c) A one will be added to the final result
d) The carry-out is ignored

Explanation: For a 4-bit parallel adder, if the carry-in is connected to a logical HIGH, one will be added to the final result as a result because carry-in gives output as 1.

2. Fast-look-ahead carry circuits found in most 4-bit full-adder circuits which ___________
a) Determine sign and magnitude
b) Reduce propagation delay
c) Add a 1 to complemented inputs
d) Increase ripple delay

Explanation: A carry-lookahead adder (CLA) is a type of adder used in digital logic. A carry-lookahead adder improves speed by reducing the amount of time required to determine carry bits. It reduces the propagation delay by making the hardware more complex. The ripple carry design is converted in such a way that carry over a group of bits of the adder becomes 2-level logic.

3. One way to make a four-bit adder to perform subtraction is by ___________
a) Inverting the output
b) Inverting the carry-in
c) Inverting the B inputs
d) Grounding the B inputs

Explanation: A adder is a digital circuit which adds bits along with a carry bit from a previous stage, thus producing 2 outputs SUM and CARRY. Since, a four bit adder has four A, four B and a carry at the input end. So, for subtraction to be performed, all the Bs terminal should be inverted.

a) It is slower than the ripple-carry adder
b) It is easier to implement logically than a full adder
c) It is faster than a ripple-carry adder

Explanation: It is faster than ripple carry adder as it reduces the propagation delay by converting the ripple carry in such a way that the carry over a group of bits of the adder becomes 2-level logic.

5. Carry lookahead logic uses the concepts of ___________
a) Inverting the inputs
b) Complementing the outputs
c) Generating and propagating carries
d) Ripple factor

Explanation: Look Ahead Carry Adder is a type of digital circuit which reduces the propagation delay. Carry lookahead logic uses the concepts of generating and propagating carries. Although in the context of a carry lookahead adder, it is most natural to think of generating and propagating in the context of binary addition, the concepts can be used more generally than this.
Sanfoundry Certification Contest of the Month is Live. 100+ Subjects. Participate Now!

a) The interconnections are more complex
b) More stages are required to a full adder
c) It is slow due to propagation time
d) All of the Mentioned

Explanation: The main disadvantage in using this type of adders is that the time delay increases as for each adder to add the carry should be generated in the previous adder, and for that to add the carry from the one before is required. However, this disadvantage is taken care of in Carry Look Ahead adder in which the ripple carry is converted in such a way that the carry over a group of bits of the adder becomes 2-level logic.

7. The carry propagation delay in 4-bit full-adder circuits ___________
a) Is cumulative for each stage and limits the speed at which arithmetic operations are performed
b) Is normally not a consideration because the delays are usually in the nanosecond range
c) Decreases in direct ratio to the total number of full-adder stages
d) Increases in direct ratio to the total number of full-adder stages but is not a factor in limiting the speed of arithmetic operations

Explanation: A full adder is a digital circuit with 3 inputs and two outputs SUM and CARRY. The carry propagation delay in 4-bit full-adder circuits is cumulative for each stage and limits the speed at which arithmetic operations are performed.

8. What is Manchester carry chain?
a) Is a chain of controlled inverter
d) Variation of a ripple carry adder

Explanation: The Manchester carry chain is a variation of the carry-lookahead adder that uses shared logic to lower the transistor count. However, the carry generating logic depends on the logic to generate the carries in the past.

9. The main disadvantage of Manchester carry chain is ___________
a) Ripple factor
b) Propagation delay
d) Both propagation delay and capacitive load

Explanation: Propagation delay is the measure of time taken by the output to go to the next state when the input is altered. One of the major downsides of the Manchester carry chain is that the capacitive load of all of these outputs, together with the resistance of the transistors causes the propagation delay to increase much more quickly than a regular carry lookahead.

10. The summing outputs of a half or full-adder are designated by which Greek symbol?
a) Omega
b) Theta
c) Lambda
d) Sigma

Explanation: The summing outputs of a half or full-adder are designated by “sigma” which is a Greek symbol. This same symbol is used to signify the Minterms in case of an SOP expression.

11. Why is a fast-look-ahead carry circuit used in the 7483 4-bit full-adder?
a) To decrease the cost
b) To make it smaller
c) To slow down the circuit
d) To speed up the circuit

Explanation: A Carry Look Ahead (CLA) Adder is a type of adder that reduce the propagation delay. A fast Carry Look Ahead Adder is more fast than a normal CLA. Since, it is easy to implement and can be implemented on any types of chip and have the capability to reduce propagation delay, which helps in increasing the speed of 7483 4-bit full-adder.

Sanfoundry Global Education & Learning Series – Digital Circuits.

To practice all areas of Digital Electronic Circuits for various tests, here is complete set of 1000+ Multiple Choice Questions and Answers.

If you find a mistake in question / option / answer, kindly take a screenshot and email to [email protected]