# Microelectronics Questions and Answers – High Frequency Model of BJT and MOSFET

This set of Microelectronics Multiple Choice Questions & Answers (MCQs) focuses on “High Frequency Model of BJT and MOSFET”.

1. In a CE stage, which capacitor faces Miller Effect in absence of Emitter degeneration and early effect?
a) The capacitor between substrate and collector
b) The capacitor between base and collector
c) The capacitor between base and emitter
d) The capacitor between base and substrate

Explanation: In absence of source degeneration, only the capacitor between the base and collector terminal faces miller effect. There capacitance between base and emitter, & substrate and collector, doesn’t happen to have a gain between it’s terminals since the emitter and the substrate is grounded.

2. In a CS, which capacitor faces Miller Effect in absence of Source degeneration and channel length modulation?
a) The capacitor between gate and source
b) The capacitor between source and drain
c) The capacitor between gate and drain
d) The capacitor between gate and substrate

Explanation: In absence of source degeneration, only the capacitor between the gate and drain terminal faces miller effect. There capacitance between the gate and source, & substrate and gate, doesn’t happen to have a gain between it’s terminals since the source and the substrate is grounded.

3. In a Bipolar transistor, what happens to the capacitor appearing between the base and the collector terminals if VBE is increased?
a) It increases
b) It decreases
c) It remains constant
d) It doesn’t exist

Explanation: The junction capacitance between the base and the collector increases if VBE is increased. This is because the diffusion capacitance is the parallel combination of the transition and the diffusion capacitances. If VBE increases, the minority carrier lifetime decreases and the incremental resistance decreases – thus, the diffusion capacitance decreases. Noting that the diffusion capacitance is less than the depletion capacitance, the overall capacitance has also decreased.

4. If the emitter doping is NA and the base doping is ND, what is the direction of electric field due to the diffusion capacitance that has appeared between them?
a) From emitter to base
b) From base to emitter
c) From base to ground
d) From emitter to ground

Explanation: We know that the electric field, inside a parallel plate capacitor, is directed in the direction of the applied electric field. This shows that the electric field will be directed from the emitter to the base since the diffusion capacitance rises due to the forward bias. If the base is grounded, the electric field will go from emitter to ground but the base need not be grounded to force the base-emitter junction to be forward biased.

5. By what factor will the depletion capacitance between base and emitter increase, if the doping concentration of each region increase by a factor of 2? Assume that the base width has been very high due to imperfection in the manufacturing process.
a) √2
b) √3
c) √5
d) 2

Explanation: We note that the diffusion capacitance for a pn junction is given by $$\sqrt{\frac {qεNaNd}{2*(Vbi+ Vr)(Na + Nd)}}$$. We can note that if we neglect the presence of collector, we find that the depletion capacitance will increase by a factor of √2.

6. In a CS stage, which capacitor faces Miller Effect in presence of Source degeneration and early effect?
a) The capacitor between gate and source
b) The capacitor between source and gate & gate and drain
c) The capacitor between gate and drain
d) The capacitor between gate and substrate & source and drain

Explanation: In presence of source degeneration, the capacitance from gate to source faces an amplification factor which is equal to that of a follower. Hence, two capacitors will face miller effect – one is between the gate and drain and the other is between the gate and source.

7. In a CE stage, which capacitor faces Miller Effect in presence of Emitter degeneration and early effect?
a) The capacitor between substrate and collector
b) The capacitor between base and collector
c) The capacitors between base and emitter & base and collector
d) The capacitor between base and substrate & base and collector

Explanation: We observe that the capacitor between the base and emitter observes a voltage gain similar to the follower stage. Hence, this along with the capacitance between base and collector will face miller effect.

8. In a MOSFET, what is the oxide capacitance between the gate and the channel when the channel is completely depleted? Note that COX is oxide/area, W & L are the width and length of the channel.
a) WLCOX
b) (W-L)2COX
c) (W2)COX
d) (W+L)2COX

Explanation: When the channel is completely depleted, the charge developed in it is primarily due to the capacitance effect of the gate oxide. Note that W, L will be controlled by the manufacturing process and L gets reduced due to the formation of source and drain. The oxide capacitance between the gate and the channel when the channel is completely depleted is WLCOX.

9. What kind of capacitance exists between the channel and the substrate, in a MOSFET, when the channel is completely depleted?
a) Forward capacitance
b) Diffusion capacitance
c) No capacitance exists
d) Depletion Capacitance

Explanation: Depletion capacitance will be developed between the channel and the substrate as the channel contains charge which is exactly opposite to the substrate.

10. What happens to the capacitance between the channel and the substrate if the doping of the substrate of a MOSFET is increased by a factor of 2?
a) It increases by a factor of √6
b) It decreases by a factor of √2
c) It increases by a factor of √(2/ln(2)
d) It increases by a factor of √5

Explanation: The capacitance between the channel and the substrate is given by WL$$\sqrt{q∈\frac {Nsub}{4\emptyset f}}$$. Note that 4Φf is the built in proportional and is equal to VT*ln(Nsub/ni). Hence, if the doping is increased by a factor of 2, the capacitance will increase by a factor of √(2/ln(2).

11. The capacitance between the source and the substrate is said to be governed by two capacitances. What are they?
a) Junction capacitance in the bottom and side of the source
b) Forward capacitance in the bottom and top of the source
c) There is no capacitance between the source and substrate; they are isolated from each other
d) Junction capacitance in the bottom and forward capacitance in the side

Explanation: Due to the lateral structure of the MOSFET, the source is surrounded by the substrate in the bottom and the side. Hence, parasitic capacitance will be developed in both of these sides. The doping of the source is opposite with that of the substrate and hence, junction capacitance will be formed.

12. How does the depletion capacitance change if the permittivity of the substrate increases by a factor of 4?
a) Increases by a factor of 2
b) Decreases by a factor of 2
c) Increases by a factor of 4
d) Increases by a factor of 4

Explanation: The depletion capacitance is proportional to √εsubstrate & hence the capacitance will increase by a factor of 2 if the permittivity increases by a factor of 4.

13. What happens to the depletion width towards the source of an NMOS if ND >> NA & NA increases by a factor of 2?
a) √5/2
b) 1/√3
c) 1/2
d) 1/√2

Explanation: If ND >> NA, we may approximate the depletion width at the MOSFET as that of a one-sided pn junction and the expression of width is $$\sqrt{\frac {2∈(Vbi+Vr)}{qNd}}$$. We readily note that the depletion width will decrease by a factor of 1/√2.

14. What happens to the depletion capacitance near the source of an NMOS if all the doping concentration increases by a factor of 2?
a) √5
b) √3
c) √2
d) 2

Explanation: The expression of the depletion capacitance near the source of an NMOS may be approximated as $$\sqrt{\frac {q\varepsilon NaNd}{2(Vbi+Vr)(Na+Nd)}}$$. We readily observe that if the concentrations are increased, the depletion capacitance will go up by a factor of √2.

15. The junction capacitance and the diffusion capacitance in the base emitter region are in ___ with each other.
a) Series
b) Parallel
c) Star with Cμ and in series
d) Delta with Cμ and in parallel

Explanation: They are parallel to each other and the junction capacitance is dominant when the BE junction is reverse biased while the diffusion capacitance is dominant when they are in forward bias.

Sanfoundry Global Education & Learning Series – Microelectronics.

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