Processor Architecture and Assembly Programming Training


Course Name
Processor Architecture and Assembly Programming Training

Course Overview
This course on Processor Architecture and Assembly Programming training focuses on the basic architecture, programming environment and instruction set of the processor and the opcode structure of Intel 64 and IA-32 processors.These training target operating-system and BIOS designers and addresses the programming environment for classes of software that host operating systems.

Target Audience

  • Application Programmers and Programmers who write operating systems or executives
  • Developers, Testers/QA and Verification Engineers who are working on or keen to know Processor Architecture and Assembly Programming

Fee, Schedule & Registration
Click Here for Processor Architecture and Assembly Programming Training course, training schedule, fee and registration information.

Processor Architecture and Assembly Programming Training Course Outline

Intel 64 and IA-32 Architectures
Brief History of Intel 64 and IA-32 Architecture
More On Specific Advances
Intel 64 and IA-32 Processor Generations
Basic Execution Environment
Modes of Operation
Overview of The Basic Execution Environment
Memory Organization
Basic Program Execution Registers
Instruction Pointer
Operand-Size and Address-Size Attributes
Operand Addressing
Data Types
Fundamental Data Types
Numeric Data Types
Pointer Data Types
Bit Field Data Type
String Data Types
Packed SIMD Data Types
BCD and Packed BCD Integers
Real Numbers and Floating-Point Formats
Overview of Floating-Point Exceptions
Instruction Set Summary
General-Purpose Instructions
X87 FPU Instructions
X87 FPU and SIMD State Management Instructions
MMX™ Instructions
SSE Instructions
SSE2 Instructions
SSE3 Instructions
Supplemental Streaming SIMD Extensions 3 (SSSE3) Instructions
SSE4 Instructions
SSE4.1 Instructions
SSE4.2 Instruction Set
Intel® Advanced Vector Extensions (Intel® AVX)
16-Bit Floating-Point Conversion
Fused-Multiply-Add (FMA)
Intel Advanced Vector Extensions 2 (Intel® AVX2)
Intel Transactional Synchronization Extensions (TSX)
System Instructions
64-Bit Mode Instructions
Virtual-Machine Extensions
Safer Mode Extensions
Procedure Calls, Interrupts, and Exceptions
Procedure Call Types
Calling Procedures Using Call and Ret
Interrupts and Exceptions
Procedure Calls For Block-Structured Languages
Programming With General-Purpose Instructions
Programming Environment For GP Instructions
Programming Environment For GP Instructions In 64-Bit Mode
Summary of GP Instructions
Programming With The X87 FPU
X87 FPU Execution Environment
X87 FPU Data Types
Floating-Point Encodings and Pseudo-Denormals
X86 FPU Instruction Set
X87 FPU Floating-Point Exception Handling
X87 FPU Floating-Point Exception Conditions
X87 FPU Exception Synchronization
Handling X87 FPU Exceptions In Software
Programming With Intel MMX Technology
Overview of MMX Technology
The MMX Technology Programming Environment
Saturation and Wraparound Modes
MMX Instructions
Compatibility With X87 FPU Architecture
Writing Applications With MMX Code
Programming With Streaming SIMD Extensions (SSE)
Overview of SSE Extensions
SSE Programming Environment
SSE Data Types
SSE Instruction Set
FXSAVE and FXRSTOR Instructions
Handling SSE Instruction Exceptions
Writing Applications With The SSE Extensions
Programming With Streaming SIMD Extensions 2 (SSE2)
Overview of SSE2 Extensions
SSE2 Programming Environment
SSE2 Data Types
SSE2 Instructions
SSE, SSE2, and SSE3 Exceptions
Writing Applications With SSE/SSE2 Extensions
Programming With SSE3, SSSE3, SSE4 and Aesni
Programming Environment and Data Types
Overview of SSE3 Instructions
SSE3 Instructions
Writing Applications With SSE3 Extensions
Overview of SSSE3 Instructions
SSSE3 Instructions
Writing Applications With SSSE3 Extensions
SSE3/SSSE3 and SSE4 Exceptions
SSE4 Overview
SSE4.1 Instruction Set
SSE4.2 Instruction Set
Writing Applications With SSE4 Extensions
Aesni Overview
Managing State Using The XSAVE Feature Set
XSAVE-Managed Features and State-Component Bitmaps
Enumeration of Cpu Support For XSAVE Instructions and XSAVE-Supported Features
Enabling The XSAVE Feature Set and XSAVE-Supported Features
XSAVE-Managed State
Operation of XSAVE
Operation of XRSTOR
Operation of XSAVEOPT
Operation of XSAVEC
Operation of XSAVES
Operation of XRSTORS
Programming With AVX, FMA and AVX2
Intel AVX Overview
Functional Overview
Detection of AVX Instructions
Fused-Multiply-Add (FMA) Extensions
Overview of AVX2
Promoted Vector Integer Instructions In AVX2
Accessing YMM Registers
Memory Alignment
Simd Floating-Point Exceptions
Writing AVX Floating-Point Exception Handlers
General Purpose Instruction Set Enhancements
Programming With Intel Transactional Synchronization Extensions
Intel Transactional Synchronization Extensions
Intel TSX Application Programming Model
I/O Port Addressing
I/O Port Hardware
I/O Address Space
I/O Instructions
Protected-Mode I/O
Ordering I/O
Processor Identification and Feature Determination
Using The CPUID Instruction

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Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He lives in Bangalore, and focuses on development of Linux Kernel, SAN Technologies, Advanced C, Data Structures & Alogrithms. Stay connected with him at LinkedIn.

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