Course Name
PCI-E – Peripheral Component Interconnect – Express Training
Course Overview
This course on PCI-E Peripheral Component Interconnect – Express training is designed for people who work on development, testing and verification of PCI-E protocol. Participants will learn the internals of PCI-E protocol that helps them with a much better understanding of their current PCI-E work.
Target Audience
- Professionals and Students who are working in Storage/Networking/IT Domain
- Developers, Testers/QA and Verification Engineers who are working on or keen to know Peripheral Component Interconnect – Express
Fee, Schedule & Registration
Click Here for PCI-E – Peripheral Component Interconnect – Express Training course, training schedule, fee and registration information.
PCI-E – Peripheral Component Interconnect – Express Training Course Outline
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PCI-E Architecture Introduction To PCI Express Predecessor Buses Compared I/O Bus Architecture Perspective The PCI Express Way Introduction to PCI Express Transactions PCI Express Device Layers Example of a Non-Posted Memory Read Transaction – Memory Read Request Phase – Completion with Data Phase Hot Plug PCI Express Performance and Data Transfer Efficiency |
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Address Spaces & Transaction Routing Two Types of Local Link Traffic – Ordered Sets – Data Link Layer Packets (DLLPs) Transaction Layer Packet Routing Basics Applying Routing Mechanisms – Address Routing – ID Routing – Implicit Routing Plug-And-Play Configuration of Routing Options |
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Packet-Based Transactions Transaction Layer Packets – TLPs Assembling And Disassembling – Device Core Requests Access to Four Spaces – TLP Transaction Variants Defined – TLP Structure Building Transactions: TLP Requests & Completions – IO Requests – Memory Requests – Configuration Requests – Completions – Message Requests Data Link Layer Packets – Types Of DLLPs – DLLPs Are Local Traffic – Receiver handling of DLLPs – Sending A Data Link Layer Packet – Fixed DLLP Packet Size: 8 Bytes – DLLP Packet Types |
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ACK/NAK Protocol Reliable Transport of TLPs Across Each Link Elements of the ACK/NAK Protocol – Transmitter Elements of the ACK/NAK Protocol – Receiver Elements of the ACK/NAK Protocol ACK/NAK DLLP Format ACK/NAK Protocol Details Error Situations Reliably Handled by ACK/NAK Protocol Recommended Priority To Schedule Packets |
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QoS/TCs/VCs and Arbitration Quality of Service – Isochronous Transaction Support – Differentiated Services Perspective on QOS/TC/VC and Arbitration Traffic Classes and Virtual Channels – VC Assignment and TC Mapping Arbitration – Virtual Channel Arbitration – Port Arbitration – Switch Arbitration |
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Flow Control Flow Control Buffers – VC Flow Control Buffer Organization – Flow Control Credits – Maximum Flow Control Buffer Size Introduction to the Flow Control Mechanism Flow Control Packets Operation of the Flow Control Model Infinite Flow Control Advertisement The Minimum Flow Control Advertisement Flow Control Initialization Flow Control Updates Following FC_INIT |
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Transaction Ordering Producer/Consumer Model Native PCI Express Ordering Rules Relaxed Ordering Modified Ordering Rules Improve Performance Support for PCI Buses and Deadlock Avoidance |
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Interrupts Methods of Interrupt Delivery – Message Signaled Interrupts – Legacy PCI Interrupt Delivery Special Consideration for Base System Peripherals |
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Error Detection and Handling PCI Express Error Management Sources of PCI Express Errors Error Classifications Baseline Error Detection and Handling Advanced Error Reporting Mechanisms |
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Physical Layer Logic Physical Layer Overview – Transmit Logic Overview – Receive Logic Overview – Physical Layer Link Active State Power Management – Link Training and Initialization Transmit Logic Details Receive Logic Details Physical Layer Error Handling |
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System Reset Fundamental Reset In-Band Reset or Hot Reset Reset Exit |
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Link Initialization & Training Ordered-Sets Used During Link Training and Initialization Link Training and Status State Machine (LTSSM) Detailed Description of LTSSM States LTSSM Related Configuration Registers |
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PCI Express Configuration PCI-Compatible Configuration Mechanism Type 0 Configuration Request Type 1 Configuration Request Initial Configuration Accesses |
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PCI Express Enumeration Enumerating a System With a Single Root Complex Enumerating a System With Multiple Root Complexes A Multifunction Device Within a Root Complex or a Switch An Endpoint Embedded in a Switch or Root Complex Memorize Your Identity Root Complex Register Blocks (RCRBs) |
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Expansion ROMs ROM Purpose—Device Can Be Used In Boot Process ROM Detection ROM Shadowing Required ROM Content Execution of Initialization Code Introduction to Open Firmware |
