This set of Software Defined Radio Multiple Choice Questions & Answers (MCQs) focuses on “Digital Architecture Tradeoffs – 1”.
1. ____ is obtained by the product of number of parallel hardware elements and clock speed.
Explanation: Millions of operation per second (MOPS) is obtained by the product of number of parallel hardware elements and clock speed. An operation (OP) is a logical transformation of data carried out by portion of hardware in one clock cycle.
2. A combination of a band and mode is called ______
a) matched pair
b) matched set
Explanation: Each combination of band and mode is a multiple personality. A personality combines RF band, channel set, air interface waveform, protocol, and related functions.
3. Which of the following is not a hardware module?
Explanation: The development of a SDR involves accurate analysis of functional and statistical structure of hardware and software. The key step in system analysis is the identification of processing resources and characterization of processing capacity of digital hardware. Memory, DSP and workstation are few examples of digital hardware.
4. ____ is a technique where multiple instructions are overlapped during execution.
c) Instruction fetching
Explanation: Pipelining is a technique where multiple instructions are overlapped during execution. Pipeline consists of many stages that vary from processor to processor. Pipelining increases the overall throughput of instruction execution.
5. ____ serves as a system control processor.
b) Bus host
Explanation: Bus host serves as a system control processor. Analog to Digital Converter is responsible for the conversion of an analog signal into a digital signal suitable for further processing. Digital Signal Processor supports real time channel processing.
6. Which of the following is not a type of digital-interconnect?
b) Dedicated interconnect
c) Wideband bus
d) Shared memory
Explanation: Dedicated interconnect, wideband bus and shared memory are different types of available digital-interconnect. In dedicated interconnect, the vendor of a board provides a suitable interconnect. Shared memory reserves a block of memory for communication. The performance of shared memory can be enhanced by operating with programmable Direct Memory Access (DMA) or equivalent hardware.
7. Interconnect efficiency is a function of ____ being transferred.
a) number of data blocks
b) size of data blocks
c) type of data blocks
d) accuracy of data blocks
Explanation: Interconnect efficiency is a function of size of data blocks being transferred. Most buses exhibit low throughput for smaller block size. In addition to block size, features such as Direct Memory Access overhead, handshaking mechanism affect the overall throughput.
8. MFLOPS stands for Millions of Fixed Point Operation per Second.
Explanation: MFLOPSstands for Millions of Floating Point Operation per Second. An operation (OP) is a logical transformation of data carried out by portion of hardware in one clock cycle. MIPS, MOPS, MFLOPS are differentiated by their logical scope.
9. Architecture of local and global memory among processors can contribute to algorithm performance.
Explanation: Architecture of local and global memory among processors can contribute to algorithm performance. Balancing high speed data flow and bandwidth reduction leads to clustering of memory and processing capacity.
10. Which of the following is the first step in FEC decoding?
a) Input bitstream synchronization
d) Symbol puncturing
Explanation: The first step in FEC decoding is input bitstream synchronization. It is followed by reversing the effect of symbol puncturing and estimation of transmitted bits. Then the resulting signal is decoded and descrambled.
11. FEC operations are ____
Explanation: Forward error control operations are bit-serial. It involves bit-level manipulations. They are usually carried out in registers of length 11, 13 etc. Additional bit-masking is required to implement FEC functions.
12. _____ interleave two systematic concatenated codes.
b) Soft codes
c) Convolution codes
d) Trellis codes
Explanation: Turbo codes interleave two systematic concatenated codes. It improves error protection. Turbo codes exhibit high performance with low complexity encoding and decoding algorithms.
13. Which of the following ASIC is preferred in IF stage?
a) FEC ASICs
b) Digital filtering ASICs
c) Transceiver ASICs
d) INFOSEC ASICs
Explanation: Digital filtering ASICs are preferred in IF stage as they perform IF-baseband frequency translation and filtering. FEC ASICs are used for encapsulation in modem entity.
14. The access of architecture level functions from component level building blocks may be called _____
a) Universal plug and play
d) Point-to-point protocol
Explanation: The integration of Application Specific Integrated Circuits in SDR necessitates a means for passing control and data information. The access of architecture level functions from component level building blocks may be called tunneling. It requires the refinement of layered virtual machine architecture.
15. Which of the following options is not an aspect of tunneling facility?
a) Definition of interface points
b) Identification of constraints
c) Identification of processing capability
d) Resolving conflicts
Explanation: The functions of the tunneling facility include the definition of interface points, use of tunneled components, identification of constraints, and resolution of conflicts. The interfaces to the application objects are described to the radio infrastructure by using Tunnel() function.
Sanfoundry Global Education & Learning Series – Software Defined Radio.
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