MSP430 Microcontroller Questions and Answers – SPI

This set of MSP430 Microcontroller Questions and Answers for Aptitude test focuses on “SPI”.

1. Is SPI a full duplex technique?
a) yes
b) no
c) cant be said
d) depends on the conditions

Explanation: Yes, SPI is a technique where a data can be transmitted/ received in both the directions.

2. The concept of SPI is based on __________
a) two counters
b) four flip flops
c) two shift registers

Explanation: The concept of the SPI is based on the two shift registers, one for the transmitter and the other is there for the receiver terminal.

3. Writing on the trailing edge of the clock pulse and reading on the leading edge of the clock pulse is done when
a) CPHA is set
b) CPHA is reset
c) CPOL is set
d) CPOL is reset

Explanation: When CPHA is reset to zero, then writing on the trailing edge of the clock pulse and reading on the leading edge of the clock pulse.

4. When CPOL=1 then,
a) clock idles high between transfers
b) clock idles low between transfers
c) bit idles high between transfers
d) bit ideals low between transfers

Explanation: When CPOL=1, clock idles high between transfers.

5. Is CPKH and CPOL the same.
a) yes
b) no
c) cant be said
d) depends on the conditions

Explanation: CPKL=CPOL and CPKH=(not CPHA).
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6. SPI with the USI can be selected by ________
a) setting the USII2C bit in the register USICTL1
b) clearing the USII2C bit in the register USICTL1
c) setting the USIPE5–7 bits in USICTL0
d) clearing the USIPE5–7 bits in USICTL0

Explanation: SPI with the USi can be selected by clearing the USII2C bit in the register USICTL1.

7. SCLK, SDO, and SDI are found ___________ on F20x3.
a) P1.0-2
b) P1.2-4
c) P1.4-6
d) P1.5-7

Explanation: SCLK, SDO, and SDI are found at P1.5-7 on F20x3.

8. Transmission and reception are made at a time in SPI?
a) true
b) false
c) cant be said
d) depends on the conditions

Explanation: Transmission and reception occur at a time in SPI. This means that a value is received only if the transmitter is active.

9. When the buffer is ________ the low power mode is__________
a) empty, reset
b) having one byte, reset
c) full, reset
d) empty, two

Explanation: When the buffer is full, the low power mode is cleared.

10. Falling edge of the SS pin denotes ________
a) end of the transfer
b) starts a new transfer
c) selects a new master
d) none of the mentioned

Explanation: Falling edge of the SS pin denotes the start of a new transfer over SPI.

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