This set of IOT Multiple Choice Questions & Answers (MCQs) focuses on “USART Protocol”.
1. What is the protocol used by USART?
Explanation: RS232C is a long established standard (“c” is the current version) that describes the physical interface and protocol for relatively low speed serial data communication between computers and relates devices.
2. USART provides a synchronous mode that is not in UART?
Explanation: Unlike a UART, USART offers the option of synchronous mode. In the program to program communication, the synchronous mode requires that each end of an exchange respond in turn without initiating a new communication.
3. Which of the following needs a clock?
a) Only Asynchronous
b) Only synchronous
c) Both synchronous and Asynchronous
d) Sometimes Synchronous
Explanation: Synchronous mode requires both data and clock. Asynchronous mode requires only data.
4. During receiving operation what does URXD have?
a) Positive edge
b) Negative edge
c) Level edge
d) Either raising or falling edge
Explanation: The receive operation is initiated by the receipt of a valid start bit. It consists of a negative edge at URXD, followed by the taking of majority vote from three samples, where 2 of the samples must be zero.
5. What is the timing of X?
a) 1/32 to 1/64 times of BRCLK
b) 1/42 to 1/63 times of BRCLK
c) 1/32 to 1/63 times of BRCLK
d) 1/32 to 1/56 times of BRCLK
Explanation: The timing of x is 1/32 to 1/63 of BRCLK, but at least BRCLK, depending on the division rate of the baud rate generation.
6. The secondary implementation uses a fixed second clock divided which is divided by ______________
Explanation: The standard implementation uses a prescalar from any clock source and a fixed second clock divider which is usually a divided by 16.
7. The USART module supports ________ multiprocessor communication modes when the asynchronous mode is used.
Explanation: The USART module supports two multiprocessor communication modes when the asynchronous mode is used. These formats can be used to transfer information between many microcomputers on the same serial link. Information is transferred as a block of frames from a particular source to one or more destinations.
8. How many asynchronous multiprocessor protocols are present?
Explanation: Both asynchronous multiprocessor protocols, the idel line and the address bit microprocessor mode allow efficient data transfer between multiple communication systems.
9. Which bit in control register defines the address bit or idle line multiprocessor protocol mode?
Explanation: The MM bit in control register defines the address bit or idle line multiprocessor protocol mode. Both formats use the wake up on transmitting, using the address feature function (TWWake bit), and on activating the RXWake bit.
10. In idle line multiprocessor mode, a precise idle period can be generated to create efficient address character identifiers.
Explanation: In idle line multiprocessor mode, a precise idle period can be generated to create efficient address character identifiers. Associated with the TXWake bit is the Wake Up Temporary (WUT) flag.
11. In synchronous operation characters must be provided on time if not ______ error occurs.
a) Overrun error
b) Underrun error
c) Framing error
d) Parity error
Explanation: USART in synchronous operation characters must be provided on time until a frame is complete, if the controlling processor does not do so, this is an underrun error, and transmission of the frame is aborted.
12. HDLC stands for ___________
a) High level Data Link Control
b) High level Data Level Control
c) High level Data Link Coordinator
d) High level Data Link Commutator
Explanation: HDLC (High-level Data Link Control) is a group of protocols or rules for transmitting data between network points (sometimes called nodes). In more technical terms, HDLC is a bit-oriented, synchronous data link layer protocol created by the International Organization for Standardization (ISO).
13. SDLC stands for ___________
a) Synchronous Data Link Control
b) Synchronous Data Level Control
c) Synchronous Data Level Coordinator
d) Synchronous Data Link Coordinator
Explanation: Synchronous Data Link Control (SDLC) is a transmission protocol used to synchronously transfer code-transparent, serial-by-bit data over a communications channel.
14. STR stands for___________
a) Synchronous Transmit Rate
b) Synchronous Target Rate
c) Synchronous Target Receive
d) Synchronous Transmit Receive
Explanation: Synchronous Transmit Receive (STR), which were with synchronous voice frequency modems. These protocols were designed to make the best use of bandwidth when modems were analog devices.
15. BSC stands for ____________
a) Binary Service Communication
b) Bandwidth Synchronous Communication
c) Binary Synchronous Communication
d) Bandwidth Service Communication
Explanation: Binary Synchronous Communication (BSC or Bisync) is an IBM character-oriented, half-duplex link protocol, announced in 1967 after the introduction of System/360. It replaced the synchronous transmit-receive (STR) protocol used with second generation computers.
Sanfoundry Global Education & Learning Series – IOT.
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