This set of IOT Multiple Choice Questions & Answers (MCQs) focuses on “Microcontroller (ARM 7)”.
1. What is the processor used by ARM7?
a) 8-bit CISC
b) 8-bit RISC
c) 32-bit CISC
d) 32-bit RISC
View Answer
Explanation: ARM7 is a group 32-bit RISC ARM processor cores licensed by ARM Holdings for microcontroller use.
2. What is the instruction set used by ARM7?
a) 16-bit instruction set
b) 32-bit instruction set
c) 64-bit instruction set
d) 8-bit instruction set
View Answer
Explanation: The instruction set used by ARM7 is a 32-bit instruction set, but some implement ARMv3. The most widely used ARM7 designs implement the ARMv4T architecture, but some implement ARM3 or ARMv5TEJ.
3. How many registers are there in ARM7?
a) 35 register( 28 GPR and 7 SPR)
b) 37 registers(28 GPR and 9 SPR)
c) 37 registers(31 GPR and 6 SPR)
d) 35 register(30 GPR and 5 SPR)
View Answer
Explanation: ARM7TDMI has 37 registers(31 GPR and 6 SPR). All these designs use a Von Neumann architecture, thus the few versions comprising a cache do not separate data and instruction caches.
4. ARM7 has an in-built debugging device?
a) True
b) False
View Answer
Explanation: Some ARM7 cores are obsolete. It had a JTAG based on-chip debugging; the preceding ARM6 cores did not support it. The “D” represented a JTAG TAP for debugging.
5. What is the capability of ARM7 f instruction for a second?
a) 110 MIPS
b) 150 MIPS
c) 125 MIPS
d) 130 MIPS
View Answer
Explanation: It is a versatile device for mobile devices and other low power electronics. This processor architecture is capable of up to 130MIPS on a typical 0.13 um process.
6. We have no use of having silicon customization?
a) True
b) False
View Answer
Explanation: It achieve custom design goals, such as higher clock speed, very low power consumption, instruction set extension, optimization for size, debug support, etc.
7. Which of the following has the same instruction set as ARM7?
a) ARM6
b) ARMv3
c) ARM71a0
d) ARMv4T
View Answer
Explanation: The original ARM7 was based on the earlier ARM6 design and used the same ARMv3 instruction set.
8. What are t, d, m, I stands for in ARM7TDMI?
a) Timer, Debug, Multiplex, ICE
b) Thumb, Debug, Multiplier, ICE
c) Timer, Debug, Modulation, IS
d) Thumb, Debug, Multiplier, ICE
View Answer
Explanation: The ARM7TDMI(ARM7 + 16 bit Thumb + JTAG Debug + fast Multiplier + enhanced ICE) processor implements the ARM4 instruction set.
9. ARM stands for _________
a) Advanced RISC Machine
b) Advanced RISC Methadology
c) Advanced Reduced Machine
d) Advanced Reduced Methadology
View Answer
Explanation: ARM, originally Acorn RISC Machine, later Advanced RISC Machine, is a family of reduced instruction set computing (RISC) architectures for computing processors.
10. What are the profiles for ARM architecture?
a) A,R
b) A,M
c) A,R,M
d) R,M
View Answer
Explanation: ARMv7 defines 3 architecture “profiles”:
A-profile, Application profile
R-profile, Real-time profile
M-profile, Microcontroller profile.
11. ARM7DI operates in which mode?
a) Big Endian
b) Little Endian
c) Both big and little Endian
d) Neither big nor little Endian
View Answer
Explanation: Big Endian configuration, when BIGEND signal is HIGH the processor treats bytes in memory as being in Big Endian format. When it is LOW memory is treated as little Endian.
12. In which of the following ARM processors virtual memory is present?
a) ARM7DI
b) ARM7TDMI-S
c) ARM7TDMI
d) ARM7EJ-S
View Answer
Explanation: ARM7DI is capable of running a virtual memory system. The abort input to the processor may be used by the memory manager to inform ARM7DI of page faults.
13. How many instructions pipelining is used in ARM7EJ-S?
a) 3-Stage
b) 4-Stage
c) 5-Stage
d)2-stage
View Answer
Explanation: A five-stage pipelining is used, consisting of Fetch, Decode, Execute, Memory, and Writeback stages. A six-stage pipelining is used in Jazelle state, consisting of Fetch, Jazelle, Execute, Memory, and Writeback stages.
14. How many bit data bus is used in ARM7EJ-s?
a) 32-bit
b) 16-bit
c) 8-bit
d) Both 16 and 32 bit
View Answer
Explanation: The ARM7EJ-s processor has a Von Neumann architecture. This feature is a single 32-bit data bus that carries both instructions and data. Only load, store, and swap instructions can access data from memory. Data can be 8- bit.
15. What is the cache memory for ARM710T?
a) 12Kb
b) 16Kb
c) 32Kb
d) 8Kb
View Answer
Explanation: The ARM710T is a general purpose 32-bit microprocessor with 8Kb cache, enlarged write buffer and memory management unit combined in a single chip.
Sanfoundry Global Education & Learning Series – IOT.
To practice all areas of IOT, here is complete set of 1000+ Multiple Choice Questions and Answers.
If you find a mistake in question / option / answer, kindly take a screenshot and email to [email protected]
- Practice Computer Science MCQs
- Check Programming Books
- Apply for Computer Science Internship
- Check Computer Science Books
- Check IOT Books
