This set of Computer Organization and Architecture Multiple Choice Questions & Answers (MCQs) focuses on “Instructions and Instruction Sequencing”.
1. RTN stands for ___________
a) Register Transfer Notation
b) Register Transmission Notation
c) Regular Transmission Notation
d) Regular Transfer Notation
View Answer
Explanation: This is the way of writing the assembly language code with the help of register notations.
2. The instruction, Add Loc,R1 in RTN is _______
a) AddSetCC Loc+R1
b) R1=Loc+R1
c) Not possible to write in RTN
d) R1<-[Loc]+[R1]
View Answer
Explanation: None.
3. Can you perform an addition on three operands simultaneously in ALN using Add instruction?
a) Yes
b) Not possible using Add, we’ve to use AddSetCC
c) Not permitted
d) None of the mentioned
View Answer
Explanation: You cannot perform an addition on three operands simultaneously because the third operand is where the result is stored.
4. The instruction, Add R1,R2,R3 in RTN is _______
a) R3=R1+R2+R3
b) R3<-[R1]+[R2]+[R3]
c) R3=[R1]+[R2]
d) R3<-[R1]+[R2]
View Answer
Explanation: In RTN the first operand is the destination and the second operand is the source.
5. In a system, which has 32 registers the register id is __________ long.
a) 16 bit
b) 8 bits
c) 5 bits
d) 6 bits
View Answer
Explanation: The ID is the name tag given to each of the registers and used to identify them.
6. The two phases of executing an instruction are __________
a) Instruction decoding and storage
b) Instruction fetch and instruction execution
c) Instruction execution and storage
d) Instruction fetch and Instruction processing
View Answer
Explanation: First, the instructions are fetched and decoded and then they’re executed and stored.
7. The Instruction fetch phase ends with _________
a) Placing the data from the address in MAR into MDR
b) Placing the address of the data into MAR
c) Completing the execution of the data and placing its storage address into MAR
d) Decoding the data in MDR and placing it in IR
View Answer
Explanation: The fetch ends with the instruction getting decoded and being placed in the IR and the PC getting incremented.
8. While using the iterative construct (Branching) in execution _____________ instruction is used to check the condition.
a) TestAndSet
b) Branch
c) TestCondn
d) None of the mentioned
View Answer
Explanation: Branch instruction is used to check the test condition and to perform the memory jump with the help of offset.
9. When using Branching, the usual sequencing of the PC is altered. A new instruction is loaded which is called as ______
a) Branch target
b) Loop target
c) Forward target
d) Jump instruction
View Answer
Explanation: None.
10. The condition flag Z is set to 1 to indicate _______
a) The operation has resulted in an error
b) The operation requires an interrupt call
c) The result is zero
d) There is no empty register available
View Answer
Explanation: This condition flag is used to check if the arithmetic operation yields a zero output.
Sanfoundry Global Education & Learning Series – Computer Organization and Architecture.
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