This set of Computer Organization and Architecture Multiple Choice Questions & Answers (MCQs) focuses on “Parallel Port”.
1. The _____ circuit enables the generation of the ASCII code when the key is pressed.
a) Generator
b) Debouncing
c) Encoder
d) Logger
View Answer
Explanation: The signal generated upon the pressing of a button is encoded by the encoder circuit into the corresponding ASCII value.
2. To overcome multiple signals being generated upon a single press of the button, we make use of ______
a) Generator circuit
b) Debouncing circuit
c) Multiplexer
d) XOR circuit
View Answer
Explanation: When the button is pressed, the contact surfaces bounce and hence it might lead to the generation of multiple signals. In order to overcome this, we use Debouncing circuits.
3. The best mode of connection between devices which need to send or receive large amounts of data over a short distance is _____
a) BUS
b) Serial port
c) Parallel port
d) Isochronous port
View Answer
Explanation: The parallel port transfers around 8 to 16 bits of data simultaneously over the lines, hence increasing transfer rates.
4. The output of the encoder circuit is/are ______
a) ASCII code
b) ASCII code and the valid signal
c) Encoded signal
d) None of the mentioned
View Answer
Explanation: The encoder outputs the ASCII value along with the valid signal which indicates that a key was pressed.
5. The disadvantage of using a parallel mode of communication is ______
a) It is costly
b) Leads to erroneous data transfer
c) Security of data
d) All of the mentioned
View Answer
Explanation: The parallel mode of data transfer is costly as it involves data being sent over parallel lines.
6. In a 32 bit processor, the A0 bit of the address line is connected to _____ of the parallel port interface.
a) Valid bit
b) Idle bit
c) Interrupt enable bit
d) Status or data register
View Answer
Explanation: None.
7. The Status flag circuit is implemented using _____
a) RS flip flop
b) D flip flop
c) JK flip flop
d) Xor circuit
View Answer
Explanation: The circuit is implemented using the edge triggered D flip flop, that is triggered on the rising edge of the valid signal.
8. In the output interface of the parallel port, along with the valid signal ______ is also sent.
a) Data
b) Idle signal
c) Interrupt
d) Acknowledge signal
View Answer
Explanation: The idle signal is used to check if the device is idle and ready to receive data.
9. DDR stands for __________
a) Data Direction Register
b) Data Decoding Register
c) Data Decoding Rate
d) None of the mentioned
View Answer
Explanation: This register is used to control the flow of data from the DATAOUT register.
10. In a general 8-bit parallel interface, the INTR line is connected to _______
a) Status and Control unit
b) DDR
c) Register select
d) None of the mentioned
View Answer
Explanation: None.
Sanfoundry Global Education & Learning Series – Computer Organisation and Architecture.
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