Computer Organization Questions and Answers – Fast Adders

This set of Computer Organization and Architecture Multiple Choice Questions & Answers (MCQs) focuses on “Fast Adders”.

1. The logic operations are simpler to implement using logic circuits.
a) True
b) False
View Answer

Answer: a
Explanation: The logic operation includes AND, OR, XOR etc.

2. The logic operations are implemented using _______ circuits.
a) Bridge
b) Logical
c) Combinatorial
d) Gate
View Answer

Answer: c
Explanation: The combinatorial circuits means, using the basic universal gates.

3. The carry generation function: ci + 1 = yici + xici + xiyi, is implemented in ____________
a) Half adders
b) Full adders
c) Ripple adders
d) Fast adders
View Answer

Answer: b
Explanation: In this the carry for the next step is generated in the previous steps operation.
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4. Which option is true regarding the carry in the ripple adders?
a) Are generated at the beginning only
b) Must travel through the configuration
c) Is generated at the end of each operation
d) None of the mentioned
View Answer

Answer: b
Explanation: The carry must pass through the configuration of the circuit till it reaches the particular step.

5. In full adders the sum circuit is implemented using ________
a) And & or gates
b) NAND gate
c) XOR
d) XNOR
View Answer

Answer: c
Explanation: sum = a ^ b ^ c (‘^’ indicates XOR operation).
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6. The usual implementation of the carry circuit involves _________
a) And & or gates
b) XOR
c) NAND
d) XNOR
View Answer

Answer: b
Explanation: In case of full and half adders this method is used.

7. A _______ gate is used to detect the occurrence of an overflow.
a) NAND
b) XOR
c) XNOR
d) AND
View Answer

Answer: b
Explanation: The overflow is detected by cn^cn-1 (‘^’ indicates XOR operation).
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8. In a normal adder circuit, the delay obtained in a generation of the output is _______
a) 2n + 2
b) 2n
c) n + 2
d) None of the mentioned
View Answer

Answer: a
Explanation: The 2n delay cause of the carry generation and the 2 delay cause of the XOR operation.

9. The final addition sum of the numbers, 0110 & 0110 is ____________
a) 1101
b) 1111
c) 1001
d) 1010
View Answer

Answer: a
Explanation: None.
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10. The delay reduced to in the carry look ahead adder is __________
a) 5
b) 8
c) 10
d) 2n
View Answer

Answer: a
Explanation: None.

Sanfoundry Global Education & Learning Series – Computer Organisation and Architecture.

If you find a mistake in question / option / answer, kindly take a screenshot and email to [email protected]

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Manish Bhojasia - Founder & CTO at Sanfoundry
Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He lives in Bangalore, and focuses on development of Linux Kernel, SAN Technologies, Advanced C, Data Structures & Alogrithms. Stay connected with him at LinkedIn.

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