This set of Computer Organization and Architecture Multiple Choice Questions & Answers (MCQs) focuses on “Asynchronous DRAM”.
1. The Reason for the disregarding of the SRAM’s is ________
a) Low Efficiency
b) High power consumption
c) High Cost
d) All of the mentioned
View Answer
Explanation: The reason for the high cost of the SRAM is because of the usage of more number of transistors.
2. The disadvantage of DRAM over SRAM is/are _______
a) Lower data storage capacities
b) Higher heat dissipation
c) The cells are not static
d) All of the mentioned
View Answer
Explanation: This means that the cells won’t hold their state indefinitely.
3. The reason for the cells to lose their state over time is ________
a) The lower voltage levels
b) Usage of capacitors to store the charge
c) Use of Shift registers
d) None of the mentioned
View Answer
Explanation: Since capacitors are used the charge dissipates over time.
4. The capacitors lose the charge over time due to ________
a) The leakage resistance of the capacitor
b) The small current in the transistor after being turned on
c) The defect of the capacitor
d) None of the mentioned
View Answer
Explanation: The capacitor loses charge due to the backward current of the transistor and due to the small resistance.
5. _________ circuit is used to restore the capacitor value.
a) Sense amplify
b) Signal amplifier
c) Delta modulator
d) None of the mentioned
View Answer
Explanation: The sense amplifier detects if the value is above or below the threshold and then restores it.
6. To reduce the number of external connections required, we make use of ______
a) De-multiplexer
b) Multiplexer
c) Encoder
d) Decoder
View Answer
Explanation: We multiplex the various address lines onto fewer pins.
7. The processor must take into account the delay in accessing the memory location, such memories are called ______
a) Delay integrated
b) Asynchronous memories
c) Synchronous memories
d) Isochronous memories
View Answer
Explanation: None.
8. To get the row address of the required data ______ is enabled.
a) CAS
b) RAS
c) CS
d) Sense/write
View Answer
Explanation: This makes the contents of the row required refreshed.
9. In order to read multiple bytes of a row at the same time, we make use of ______
a) Latch
b) Shift register
c) Cache
d) Memory extension
View Answer
Explanation: The latch makes it easy to ready multiple bytes of data of the same row simultaneously by just giving the consecutive column address.
10. The block transfer capability of the DRAM is called ________
a) Burst mode
b) Block mode
c) Fast page mode
d) Fast frame mode
View Answer
Explanation: None.
Sanfoundry Global Education & Learning Series – Computer Organisation and Architecture.
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