Computer Organization Questions and Answers – ARM Architecture – 1

This set of Computer Organization and Architecture Multiple Choice Questions & Answers (MCQs) focuses on “ARM Architecture – 1”.

1. ARM stands for _____________
a) Advanced Rate Machines
b) Advanced RISC Machines
c) Artificial Running Machines
d) Aviary Running Machines
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2. The main importance of ARM micro-processors is providing operation with ______
a) Low cost and low power consumption
b) Higher degree of multi-tasking
c) Lower error or glitches
d) Efficient memory management
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3. ARM processors where basically designed for _______
a) Main frame systems
b) Distributed systems
c) Mobile systems
d) Super computers
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4. The ARM processors don’t support Byte addressability.
a) True
b) False
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5. The address space in ARM is ___________
a) 2²⁴
b) 2⁶⁴
c) 2¹⁶
d) 2³²
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6. The address system supported by ARM systems is/are ___________
a) Little Endian
b) Big Endian
c) X-Little Endian
d) Both Little & Big Endian
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7. Memory can be accessed in ARM systems by __________ instructions.
i) Store
ii) MOVE
iii) Load
iv) arithmetic
v) logical
a) i, ii, iii
b) i, ii
c) i, iv, v
d) iii, iv, v
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8. RISC stands for _________
a) Restricted Instruction Sequencing Computer
b) Restricted Instruction Sequential Compiler
c) Reduced Instruction Set Computer
d) Reduced Induction Set Computer
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9. In the ARM, PC is implemented using ___________
a) Caches
b) Heaps
c) General purpose register
d) Stack
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10. The additional duplicate register used in ARM machines are called as _______
a) Copied-registers
b) Banked registers
c) EXtra registers
d) Extential registers
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11. The banked registers are used for ______
a) Switching between supervisor and interrupt mode
b) Extended storing
c) Same as other general purpose registers
d) None of the mentioned
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12. Each instruction in ARM machines is encoded into __________ Word.
a) 2 byte
b) 3 byte
c) 4 byte
d) 8 byte
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13. All instructions in ARM are conditionally executed.
a) True
b) False
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14. The addressing mode where the EA of the operand is the contents of Rn is ______
a) Pre-indexed mode
b) Pre-indexed with write back mode
c) Post-indexed mode
d) None of the mentioned
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15. The effective address of the instruction written in Post-indexed mode, MOVE[Rn]+Rm is _______
a) EA = [Rn]
b) EA = [Rn + Rm]
c) EA = [Rn] + Rm
d) EA = [Rm] + Rn
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Sanfoundry Global Education & Learning Series – Computer Organization and Architecture.