This set of Tough VHDL Questions and Answers focuses on “Implementing Combinational Circuits with VHDL – 2”. 1. The process statement used in combinational circuits is called ______ process. a) Combinational b) Clocked c) Unclocked d) Sequential 2. Why we need to include all the input signals in the sensitivity list of the process? a)
This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Implementing Combinational Circuits with VHDL – 1”. 1. Which of the following is a not a characteristics of combinational circuits? a) The output of combinational circuit depends on present input b) There is no use of clock signal in combinational circuits c) The
This set of Tricky VHDL Questions and Answers focuses on “Implementing Logic Functions with VHDL – 2”. 1. What do you use to perform basic logic functions in VHDL while creating concurrent code? a) Operators b) If statement c) PROCESS d) GENERATE 2. In the implementation of following function by using NAND keyword only, can
This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Implementing Logic Functions with VHDL – 1”. 1. Which of the following represents the correct order? a) Given function, optimized function, implementation b) Optimized function, implementation, given function c) Implementation, optimized function, given function d) Given function, implementation, optimized function 2. Which of
This set of VHDL written test Questions & Answers focuses on “Implementing Sequential Circuits with VHDL”. 1. A sequential logic can’t be executed by concurrent statements only. a) True b) False 2. Which of the following sequential circuit doesn’t need a clock signal? a) Flip flop b) Asynchronous counter c) Shift register d) Latch 3.
This set of Basic VHDL Questions and Answers focuses on “Implementing Gates with Different Modelling – 2”. 1. What is the minimum number of NAND gates required to implement an EXOR gate? a) 2 b) 3 c) 4 d) 5 2. Which of the following logic describes the EXOR gate? a) y <= ((not a)
This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Implementing Gates with Different Modelling – 1”. 1. Which of the following is a basic building block of a digital logic? a) Wires b) Nets c) Gates d) Flip-flops 2. Which of the following gate is a universal gate? a) AND b) NAND
This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Flattening and Factoring of Functions”. 1. What is the process of flattening? a) Converting an optimized function to unoptimized form b) Converting a Boolean function to PAL format c) Converting a Boolean function to PLA format d) Converting a Boolean function to POS
This set of VHDL Problems focuses on “All Keywords in VHDL – 3”. 1. The use of NEXT in VHDL is similar to _________ in C. a) Break b) Continue c) Exit d) Do 2. NULL keyword is most of the time useful with _______ part of _______ statement. a) IF, IF b) ELSIF, IF
This set of VHDL Assessment Questions and Answers focuses on “All Keywords in VHDL – 2”. 1. When the keyword GUARDED is used, it is always mandatory that the statements inside will be executed concurrently. a) True b) False 2. Among the following, with which keyword MAP is generally used? a) IS b) PORT c)
