This set of Analog Circuits Multiple Choice Questions & Answers (MCQs) focuses on “MOSFET Amplifier with CS Configuration – 1”.

1. Neglecting Channel Length Modulation, what is the voltage gain from the gate to the drain of M1?

a) g_{m} * R_{1}

b) g_{m} * 2R_{1}

c) g_{m} * R_{1} || R_{O}

d) 3g_{m} * R_{1}

View Answer

Explanation: We construct the r

_{π}model and find that the voltage gain from the gate to the drain of the MOSFET is g

_{m}* R

_{1}. Since Channel Length Modulation is neglected, the voltage gain won’t be g

_{m}* R

_{1}|| R

_{O}.

2. In the following C.S. stage shown below, what is the transconductance?

a) \(\frac{1}{2}\)µ_{n}C_{ox}*(W/L)(V_{1}-V_{th})

b) 3µ_{n}C_{ox}*(W/L)(V_{1}-V_{th})

c) µ_{n}C_{ox}*(W/L)(V_{1}-V_{th})

d) 2µ_{n}C_{ox}*(W/L)(V_{1}-V_{th})

View Answer

Explanation: The transconductance is the ratio of a small change in the output current due to a small change in the input voltage. By differentiating the equation relating the current to the input voltage of a MOSFET with respect to the input voltage, we’ll get \(\frac{1}{2}\)µ

_{n}C

_{ox}*(W/L)(V

_{1}-V

_{th}).

3. In the following C.S. stage shown below, what is the input impedance (ideally) if channel length modulation is neglected?

a) Infinite

b) Very high

c) Very low

d) Cannot be determined

View Answer

Explanation: Ideally, the input impedance while looking into the gate of the MOSFET is infinite. This is because of the SiO2 layer which behaves as an insulator.

4. In the following C.S. stage shown below, what is the input impedance if λ>0?

a) Infinite

b) 0

c) Very low

d) r_{o}

View Answer

Explanation: The input impedance of the C.S. stage, i.e. the impedance looking into the gate of M1 is always infinite. Hence, in presence of early effect, the input impedance remains infinite.

5. In the following C.S. stage shown below, what is the output impedance if λ>0?

a) r_{o}

b) 0

c) R_{1}

d) R_{1} || r_{o}

View Answer

Explanation: To find the output impedance, we perform a small signal analysis with the help of our r

_{π}model. After placing every voltage source (V

_{cc}and V

_{1}) to ground, we connect a simple voltage source at the drain node. Thereafter, the ratio of applied voltage to input current gives us the impedance looking into the drain which is r

_{o}. But this voltage will be applied in parallel to R1. Hence the total output impedance is R

_{1}|| r

_{o}.

6. In the following C.S. stage shown below, what is the output impedance, if channel length modulation is neglected?

a) 2r_{o}

b) 5

c) R_{1}

d) 0

View Answer

Explanation: If the early effect is neglected, r

_{o}–> ∞ and hence, the output impedance is only R

_{1}. This is inferred by performing the small signal analysis at the output node or the drain of the M1.

7. In the following C.S. stage shown below, what is the voltage gain from the gate to the drain of M1 if λ>0?

a) g_{m} * r_{o}

b) g_{m} * 2R_{1}

c) g_{m} * R_{1}||r_{o}

d) g_{m} * R_{1}

View Answer

Explanation: This is easily observable by performing a small signal analysis at the output of the C.S. stage. We need to turn off all voltage sources, Vcc mainly, and give a small input at the gate. Thereby, the voltage gain becomes g

_{m}* R

_{1}||r

_{o}. The presence of early effect reduces the gain a bit and deviates M1 from its ideal characteristics.

8. If the output voltage is sensed at the collector, which of the following option perfectly describes the stage shown below?

a) A degenerated C.S. stage

b) A C.S. stage

c) A shunted C.S. stage

d) An open C.S. stage

View Answer

Explanation: The above shown stage is a degenerated CS stage. This stage is called so because the current source connected at the source of M

_{1}reduces the total gain of the CS stage. The current source provides a finite output impedance which is connected the source. Thereby, the overall gain decreases.

9. What is the overall input resistance of the CS stage shown below?

a) R_{3}

b) R_{3} || R_{1}

c) 2 * R_{3}

d) Infinite

View Answer

Explanation: By performing a simple small signal analysis, we find that the input resistance is simply R

_{3}. The impedance is not infinite since we have a resistor between the gate and the input voltage.

10. If the output impedance of the current source is Ri, what is the output impedance of the CS stage shown below, if channel length modulation is neglected?

a) (1 + g_{m} * (R_{1} || R_{2})) * R_{i} + (R_{1} || R_{2})

b) {R_{1} * (R_{2} + r_{o})} || R_{i}

c) R_{1} || R_{2}

d) 0

View Answer

Explanation: We calculate the output impedance by shorting the two voltage sources to ground. Thereafter, as we apply a simple step input at the output node, i.e. the collector node, we’ll find that the total impedance at connected to the drain of M1 is nothing but (1 + g

_{m}* (R

_{1}|| R

_{2})) * R

_{i}+ (R

_{1}|| R

_{2}) where g

_{m}is the transconductance of M

_{1}, R

_{1}|| R

_{2}is the total resistance connected at the drain and R

_{i}is the total resistance connected at the source. The output impedance would’ve been R

_{1}|| R

_{2}if the current source was absent.

11. If the transconductance of M_{1} is 5S, voltage gain for the following degenerated CS stage is _____

a) 2.45

b) 1.25

c) 1.45

d) 2.25

View Answer

Explanation: The voltage gain for a degenerated CS stage is \(\frac{-Rd}{(\frac{1}{gm} + Rs)}\). Hence, after putting the values, we get 5/4 and hence the answer becomes 1.25. R

_{d}is the total resistance connected to the drain of the M

_{1}while R

_{s}is the total resistance connected to the source of the M

_{1}.

12. If both the MOSFET’s are identical, what is the voltage gain from V_{1} to node S?

a) V_{cc} – 2R_{1} * µ_{n} C_{ox} * (W/L) * (V_{1}-V_{th})^{2}

b) V_{cc} R_{1} * \(\frac{1}{2}\)µ_{n} C_{ox} (W/L) * (V_{1}-V_{th})^{2}

c) V_{cc} – R_{1} * µ_{n} C_{ox} (W/L) * (V_{1}-V_{th})^{2}

d) V_{cc} – 4R_{1} * \(\frac{1}{2}\)µ_{n} C_{ox} * (W/L) * (V_{1}-V_{th})^{2}

View Answer

Explanation: Since M

_{1}and M

_{2}receive the same bias voltage V

_{1}, the current generated by both the MOSFET’s are same i.e. \(\frac{1}{2}\)µ

_{n}C

_{ox}(W/L) * (V

_{1}-V

_{th})

^{2}. Both the currents enter node S and hence the voltage at node S is V

_{cc}R

_{1}* \(\frac{1}{2}\)µ

_{n}C

_{ox}(W/L) * (V

_{1}-V

_{th})

^{2}.

13. If both the MOSFET’s are identical and have channel length modulation, what is the output impedance at node S?

a) R_{1} || r_{o1} || r_{o2}

b) R_{1} + (r_{o1} || r_{o2})

c) R_{1} + (r_{o1} + r_{o2})

d) R_{1} || (r_{o1} + r_{o2})

View Answer

Explanation: If we perform a small signal analysis at node S, we will find that three resistors are connected from node S to ground. They are R

_{1}, and the resistances appearing between source and drain of the MOSFET’s due to channel length modulation ie r

_{o1}and r

_{o2}. Hence, the output resistance is R

_{1}|| r

_{o1}|| r

_{o2}.

14. If the internal resistance of the current source is finite, what will happen to the voltage gain. for the following C.S. stage, if K is doubled?

a) The voltage gain reduces by 1/2

b) The voltage gain remains the same

c) The voltage gain increases

d) The voltage gain decreases

View Answer

Explanation: The dependent current source has a variable resistance. If K doubles, the magnitude of current provided by the current source doubles, and thus, the total resistance connected to the source of M1 reduces by 2. By using the expression of voltage gain, \(\frac{-Rd}{(\frac{1}{gm} + Rs)}\), we find that a decrease in Rs leads to an increase in the voltage gain.

15. If Channel Length Modulation is present and g_{m} is the transconductance of M_{1}, what happens to the output resistance of for a fixed V_{2} in the following circuit?

a) (1 + (g_{m} * r_{o})) * R_{s} + r_{o}

b) (1 + (g_{m} * r_{o})) * r_{o} + R_{s}

c) (r_{o} + 2) * R_{s}

d) (1 + (g_{m} * r_{o})) * R_{s}

View Answer

Explanation: By performing a small signal analysis of the following circuit, we find that the output impedance of the circuit is simply (1 + (g

_{m}* r

_{o})) * R

_{s}+ r

_{o}. For doing this analysis, we have to short V

_{1}and V

_{2}to ground. Thereafter, we place a voltage source at the input node and measure current. The impedance measured will be the output impedance which is (1 + (g

_{m}* r

_{o})) * R

_{s}+ r

_{o}.

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