MOSFET Amplifier - CS Configuration Questions and Answers

This set of Analog Circuits Multiple Choice Questions & Answers (MCQs) focuses on “MOSFET Amplifier with CS Configuration – 1”.

1. Neglecting Channel Length Modulation, what is the voltage gain from the gate to the drain of M1?

a) g_m * R₁
b) g_m * 2R₁
c) g_m * R₁ || R_O
d) 3g_m * R₁
View Answer

Answer: a
Explanation: We construct the r_π model and find that the voltage gain from the gate to the drain of the MOSFET is g_m * R₁. Since Channel Length Modulation is neglected, the voltage gain won’t be g_m * R₁ || R_O.

2. In the following C.S. stage shown below, what is the transconductance?

a) \(\frac{1}{2}\)µ_nC_ox*(W/L)(V₁-V_th)
b) 3µ_nC_ox*(W/L)(V₁-V_th)
c) µ_nC_ox*(W/L)(V₁-V_th)
d) 2µ_nC_ox*(W/L)(V₁-V_th)
View Answer

Answer: a
Explanation: The transconductance is the ratio of a small change in the output current due to a small change in the input voltage. By differentiating the equation relating the current to the input voltage of a MOSFET with respect to the input voltage, we’ll get \(\frac{1}{2}\)µ_nC_ox*(W/L)(V₁-V_th).

3. In the following C.S. stage shown below, what is the input impedance (ideally) if channel length modulation is neglected?

a) Infinite
b) Very high
c) Very low
d) Cannot be determined
View Answer

Answer: a
Explanation: Ideally, the input impedance while looking into the gate of the MOSFET is infinite. This is because of the SiO2 layer which behaves as an insulator.

4. In the following C.S. stage shown below, what is the input impedance if λ>0?
View Answer

Answer: a
Explanation: The input impedance of the C.S. stage, i.e. the impedance looking into the gate of M1 is always infinite. Hence, in presence of early effect, the input impedance remains infinite.

5. In the following C.S. stage shown below, what is the output impedance if λ>0?
View Answer

Answer: d
Explanation: To find the output impedance, we perform a small signal analysis with the help of our r_π model. After placing every voltage source (V_cc and V₁) to ground, we connect a simple voltage source at the drain node. Thereafter, the ratio of applied voltage to input current gives us the impedance looking into the drain which is r_o. But this voltage will be applied in parallel to R1. Hence the total output impedance is R₁ || r_o.

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6. In the following C.S. stage shown below, what is the output impedance, if channel length modulation is neglected?

a) 2r_o
b) 5
c) R₁
d) 0
View Answer

Answer: c
Explanation: If the early effect is neglected, r_o –> ∞ and hence, the output impedance is only R₁. This is inferred by performing the small signal analysis at the output node or the drain of the M1.

7. In the following C.S. stage shown below, what is the voltage gain from the gate to the drain of M1 if λ>0?
View Answer

Answer: c
Explanation: This is easily observable by performing a small signal analysis at the output of the C.S. stage. We need to turn off all voltage sources, Vcc mainly, and give a small input at the gate. Thereby, the voltage gain becomes g_m * R₁||r_o. The presence of early effect reduces the gain a bit and deviates M1 from its ideal characteristics.

8. If the output voltage is sensed at the collector, which of the following option perfectly describes the stage shown below?

a) A degenerated C.S. stage
b) A C.S. stage
c) A shunted C.S. stage
d) An open C.S. stage
View Answer

Answer: a
Explanation: The above shown stage is a degenerated CS stage. This stage is called so because the current source connected at the source of M₁ reduces the total gain of the CS stage. The current source provides a finite output impedance which is connected the source. Thereby, the overall gain decreases.

9. What is the overall input resistance of the CS stage shown below?

a) R₃
b) R₃ || R₁
c) 2 * R₃
d) Infinite
View Answer

Answer: a
Explanation: By performing a simple small signal analysis, we find that the input resistance is simply R₃. The impedance is not infinite since we have a resistor between the gate and the input voltage.

10. If the output impedance of the current source is Ri, what is the output impedance of the CS stage shown below, if channel length modulation is neglected?

a) (1 + g_m * (R₁ || R₂)) * R_i + (R₁ || R₂)
b) {R₁ * (R₂ + r_o)} || R_i
c) R₁ || R₂
d) 0
View Answer

Answer: a
Explanation: We calculate the output impedance by shorting the two voltage sources to ground. Thereafter, as we apply a simple step input at the output node, i.e. the collector node, we’ll find that the total impedance at connected to the drain of M1 is nothing but (1 + g_m * (R₁ || R₂)) * R_i + (R₁ || R₂) where g_m is the transconductance of M₁, R₁ || R₂ is the total resistance connected at the drain and R_i is the total resistance connected at the source. The output impedance would’ve been R₁ || R₂ if the current source was absent.

11. If the transconductance of M₁ is 5S, voltage gain for the following degenerated CS stage is _____

a) 2.45
b) 1.25
c) 1.45
d) 2.25
View Answer

Answer: b
Explanation: The voltage gain for a degenerated CS stage is \(\frac{-Rd}{(\frac{1}{gm} + Rs)}\). Hence, after putting the values, we get 5/4 and hence the answer becomes 1.25. R_d is the total resistance connected to the drain of the M₁ while R_s is the total resistance connected to the source of the M₁.

12. If both the MOSFET’s are identical, what is the voltage gain from V₁ to node S?

a) V_cc – 2R₁ * µ_n C_ox * (W/L) * (V₁-V_th)²
b) V_cc R₁ * \(\frac{1}{2}\)µ_n C_ox (W/L) * (V₁-V_th)²
c) V_cc – R₁ * µ_n C_ox (W/L) * (V₁-V_th)²
d) V_cc – 4R₁ * \(\frac{1}{2}\)µ_n C_ox * (W/L) * (V₁-V_th)²
View Answer

Answer: c
Explanation: Since M₁ and M₂ receive the same bias voltage V₁, the current generated by both the MOSFET’s are same i.e. \(\frac{1}{2}\)µ_n C_ox (W/L) * (V₁-V_th)². Both the currents enter node S and hence the voltage at node S is V_cc R₁ * \(\frac{1}{2}\)µ_n C_ox (W/L) * (V₁-V_th)².

13. If both the MOSFET’s are identical and have channel length modulation, what is the output impedance at node S?

a) R₁ || r_o1 || r_o2
b) R₁ + (r_o1 || r_o2)
c) R₁ + (r_o1 + r_o2)
d) R₁ || (r_o1 + r_o2)
View Answer

Answer: a
Explanation: If we perform a small signal analysis at node S, we will find that three resistors are connected from node S to ground. They are R₁, and the resistances appearing between source and drain of the MOSFET’s due to channel length modulation ie r_o1 and r_o2. Hence, the output resistance is R₁ || r_o1 || r_o2.

14. If the internal resistance of the current source is finite, what will happen to the voltage gain. for the following C.S. stage, if K is doubled?

a) The voltage gain reduces by 1/2
b) The voltage gain remains the same
c) The voltage gain increases
d) The voltage gain decreases
View Answer

Answer: b
Explanation: The dependent current source has a variable resistance. If K doubles, the magnitude of current provided by the current source doubles, and thus, the total resistance connected to the source of M1 reduces by 2. By using the expression of voltage gain, \(\frac{-Rd}{(\frac{1}{gm} + Rs)}\), we find that a decrease in Rs leads to an increase in the voltage gain.

15. If Channel Length Modulation is present and g_m is the transconductance of M₁, what happens to the output resistance of for a fixed V₂ in the following circuit?

a) (1 + (g_m * r_o)) * R_s + r_o
b) (1 + (g_m * r_o)) * r_o + R_s
c) (r_o + 2) * R_s
d) (1 + (g_m * r_o)) * R_s
View Answer

Answer: a
Explanation: By performing a small signal analysis of the following circuit, we find that the output impedance of the circuit is simply (1 + (g_m * r_o)) * R_s + r_o. For doing this analysis, we have to short V₁ and V₂ to ground. Thereafter, we place a voltage source at the input node and measure current. The impedance measured will be the output impedance which is (1 + (g_m * r_o)) * R_s + r_o.

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