# Analog Circuits Questions and Answers – Biasing of JFET and MOSFET

This set of Analog Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Biasing of JFET and MOSFET”.

1. Which of the following statements are true?

P: JFET is biased to operate it in active region
Q: MOSFET is biased to operate it in saturation region


a) Both P and Q are correct
b) P is correct and Q is incorrect
c) P is incorrect and Q is correct
d) Both P and Q are incorrect

Explanation: While transistors are biased to work in the active region, to act as amplifiers, FET devices are instead biased in the saturation region to work as an amplifier, whether it be a JFET or a MOSFET. In saturation, current IDS changes with respect to VGS, and small changes in VGS cause proportionate changes in IDS, and the device can act as an amplifier.

2. In the given situation for n-channel JFET, we get drain-to-source current is 5mA. What is the current when VGS = – 6V?

a) 5 mA
b) 0.5A
c) 0.125 A
d) 0.5A

Explanation: IDS = IDSS(1-VGS/VP)2
When VGS = 0, IDSS = IDS = 5mA
When VGS = -6V, IDS = 5mA(1 + 4)2
IDS = 5 x 25 = 125 mA.

3. Consider the following circuit. Given that VDD = 15V, VP = 2V, and IDS = 3mA, to bias the circuit properly, select the proper statement.

a) RD < 6kΩ
b) RD > 6kΩ
c) RD > 4kΩ
d) RD < 4kΩ

Explanation: In given circuit, VGS = -5V
VDS = VDD – IDSRD
To bias properly VDS > |VP| – |VGS|
VDS > -3
15 – 3mA*RD > -3
-3mA*RD > -18
RD < 6kΩ.

4. Consider the circuit shown. VDS=3 V. If IDS=2mA, find VDD to bias circuit.

a) -30V
b) 30V
c) 33V
d) Any value of voltage less than 12 V

Explanation: VDS = VDD – IDS(10k + 5k)
3 = VDD – 2(15)
3 = VDD – 30
VDD = 33 V.

5. To bias a e-MOSFET ___________
a) we can use either gate bias or a voltage divider bias circuit
b) we can use either gate bias or a self bias circuit
c) we can use either self bias or a voltage divider bias circuit
d) we can use any type of bias circuit

Explanation: To bias an e-MOSFET, we cannot use a self bias circuit because the gate to source voltage for such a circuit is zero. Thus, no channel is formed and without the channel, the MOSFET doesn’t work properly. If self bias circuit is used, then D-MOSFET can be operated in depletion mode.

6. Consider the following circuit. Process transconductance parameter = 0.50 mA/V2, W/L=1, Threshold voltage = 3V, VDD = 20V. Find the operating point of circuit.

a) 20V, 25mA
b) 13V, 22mA
c) 12.72V, 23.61mA
d) 20V, 23.61mA

Explanation: IDS = [k’W/L(VGS – VT)2]/2
VGS = 20 x 35/55 = 12.72 V
IDS = 0.25 (9.72)2
IDS = 23.61 mA.

7. Given VDD = 25V, VP = -3V. When VGS = -3V, IDS = 10mA. Find the operating point of the circuit.

a) -3.83V, 0.766mA
b) -2.345V, 0.469mA
c) 3.83V, 0.469mA
d) 2.3V, 0.7mA

Explanation: When VGS = VP then IDSS = IDS = 10mA
Also, in above circuit, VGS = -IDSRS = – IDSx5k
Thus, IDS = IDSS(1-VGS/VP)2
Solving we get, IDS = 0.766mA, 0.469mA
Thus we get VGS = -3.83V, -2.345V
However, VGS should lie between 0 and VP.

8. Consider the following circuit. IDSS = 2mA, VDD = 30V. Find R, given that VP = – 2V.

a) 10kΩ
b) 4kΩ
c) 2kΩ
d) 5kΩ

Explanation: IDSS = 2mA
IDS = (VDD – 15)/50k = 0.3mA
VGS = VP[1 – $$\sqrt{\frac{I_{DS}}{D_{SS}}}$$]
VGS = -2 x (1 – $$\sqrt{.15}$$) = – 1.22V
Thus, VGS + IDS x (R) = 0
R = 1.22/0.3mA = 4kΩ.

9. Which of the following statements are true?

A: In a self bias circuit, the current IDS is not stable.
B: Source capacitance, CS, parallel to RS, reduces stability.


a) Both statements are correct and B is the correct reasoning
b) Both statements are correct but B is not the correct reason for it
c) Statement A is correct while statement B is wrong
d) Both statements are incorrect

Explanation: In a self bias circuit, the current IDS is stable due to the presence of source resistance RS in the circuit. The source resistance helps provide negative feedback to keep current stable. Capacitor CS is a bypass capacitor to prevent decrease in voltage gain.

10. For a MOSFET, the pinch-off voltage is -3V. Gate to source voltage is 20V. W/L ratio is 5. Process transconductance parameter is 40μA/V2. Find drain to source current in saturation.
a) 0.10 mA
b) 0.05mA
c) – 0.05mA
d) – 50A

Explanation: ISD = k’W(VSG – |VT|)2/2L
ISD = 20*5*(-20-3)2 = 52900μA = 0.05mA.

Sanfoundry Global Education & Learning Series – Analog Circuits.

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