This set of Analog Circuits Questions and Answers for Aptitude test focuses on “MOSFET Amplifier with CS Configuration – 2”.

1. What is the input impedance of the following C.S. stage?

a) R_{2} || R_{3}

b) R_{1} || (R_{2} + R_{3})

c) (R_{1} || R_{2}) + R_{3}

d) R_{1} + (R_{2} || R_{3})

View Answer

Explanation: The input impedance can be calculated by performing a small signal analysis at the input side ie the Gate of M

_{1}. We need to set V

_{cc}and V

_{1}to 0 and place a voltage source at the node after R

_{1}. Henceforth we find that R

_{2}and R

_{3}are simply connected from the same node to ground so they are parallel to each other. Note that by input impedance of the C.S. stage, we refer to the impedance seen by the signal after it crosses R

_{1}.

2. Neglecting Channel Length Modulation, what is the output impedance of the following C.S. stage?

a) R_{4}

b) R_{4} || R_{2}

c) R_{4} || (R_{2} + R_{3})

d) R_{4} || [(R_{2} + R_{3}) || R_{1}]

View Answer

Explanation: The output impedance is calculated by a simple small signal analysis. We set V

_{cc}and V

_{1}to 0 and place a voltage source at the output node. We find that only R

_{4}is the output impedance. Note that even if R

_{2}seems to be connected to R

_{4}, it doesn’t affect the output impedance since during small signal analysis, the node where R

_{2}and R

_{4}meets, is set to ground.

3. In the following C.S. stage, what is the gate voltage appearing across M_{1}?

a) V_{1} * [(R_{2} || R_{3}) / (R_{1} || R_{2} || R_{3})]

b) V_{1} * [(R_{2} + R_{3}) / {R_{1} + R_{2}) || R_{3}}]

c) V_{1} * [(R_{2} + R_{3}) / (R_{1} + R_{2} + R_{3})]

d) V_{1} * [(R_{2} || R_{3}) / {R_{1} + (R_{2} ||R_{3}}]

View Answer

Explanation: The Thevenin resistance seen by the input voltage V

_{1}is R

_{1}+ (R

_{2}|| R

_{3}). The Thevenin resistance is calculated by setting V

_{cc}to 0 and hence calculating the current entering the C.S. stage. After finding the Thevenin Resistance, it is found that the voltage drop across the gate of M1 is due to a potential divider between R1 and (R

_{2}|| R

_{3}) where the voltage across (R

_{2}|| R

_{3}) is truly the gate voltage. Hence, the total gate voltage V1 is attenuated and becomes V

_{1}* [(R

_{2}|| R

_{3}) / {R

_{1}+ (R

_{2}||R

_{3}}] .

4. If an NMOS is degenerated by a resistor in series with the source, what will happen to the output resistance?

a) It increases

b) It decreases

c) It remains same

d) Cannot be determined

View Answer

Explanation: This is a fact derived by performing the small signal analysis of a degenerated C.S. stage. The output impedance increases if we degenerate the MOSFET and this further increases the linearity of operation.

5. If we have 3 resistors of 1k, 2k and 3k, how should they be used amongst R_{1}, R_{2} and R_{3} to get the maximum gate voltage in the following C.S. stage?

a) R_{1} = 1k, R_{2} = 2k, R_{3} = 3k

b) R_{1} = 3k, R_{2} = 2k, R_{3} = 1k

c) R_{1} = 2k, R_{2} = 1k, R_{3} = 3k

d) R_{1} = 3k, R_{2} = 1k, R_{3} = 2k

View Answer

Explanation: The Thevenin resistance seen by V

_{1}is R

_{1}+ (R

_{2}|| R

_{3}). The gate voltage is a result of V

_{1}going through a potential divider of R1 and (R

_{2}|| R

_{3}) where the voltage across (R

_{2}|| R

_{3}) is essentially the gate voltage ie V

_{1}* [(R

_{2}|| R

_{3}) / { R

_{1}|| R

_{2}|| R

_{3}) }]. Hence, we need to maximize (R

_{2}|| R

_{3}) which is possible if R

_{2}=2k and R

_{3}=3k. This implies R

_{1}has to be equal to 1k.

6. If V_{th} is .45V, what is the output voltage for the following C.S. stage?

a) 4.7 V

b) 3.9 V

c) 2.1 V

d) 3.5 V

View Answer

Explanation: Firstly, we know that the voltage gain from the gate to the source is g

_{m}* R

_{4}. We observe that V

_{g}is V

_{in}* [(R

_{2}|| R

_{3}) / {R

_{1}|| R

_{2}|| R

_{3}}, where V

_{in}is 1v and the values of R

_{1}, R

_{2}and R

_{3}are provided, which is roughly equal to .55V. This .55V is getting amplified by a factor of g

_{m}*R

_{4}. Now, V

_{out}is related to I

_{d}, the drain current, as V

_{dd}– I

_{d}*R

_{4}. Again, we know that g

_{m}= 2I

_{d}/V

_{gs}-V

_{th}. So, we have 2 equations as follows:

i. V

_{out}= g

_{m}*R

_{4}= 2*I

_{d}/(V

_{gs}– V

_{th})*R

_{4}

ii. V

_{out}= V

_{dd}– I

_{d}* R

_{4}

We have the values of all the parameters. Solving for V

_{out}will yield Vout as 4.7V.

7. What is the output voltage in the following C.S. stage?

a) 5 V

b) 0 V

c) 2.5 V

d) 3 V

View Answer

Explanation: There is no resistor placed between the drain and the supply voltage, V

_{dd}. Hence, V

_{out}is nothing but 5V.

8. What is the role of the capacitor in the following circuit?

a) Increasing the gain

b) Decreasing the gain

c) Has not role

d) Decreases the output impedance

View Answer

Explanation: We note that this circuit is an example of a degenerated C.S. stage. If the impedance connected at the source terminal is very low, the voltage gain of the circuit increases. The capacitor is called a bypass capacitor as it helps to provide a path of much less resistance than R5. The magnitude of capacitance can be controlled, to an extent, according to the frequency of operation.

9. Coupling capacitors provide D.C. coupling during biasing of transistors.

a) True

b) False

View Answer

Explanation: Capacitors always block D.C. signals. In fact, they provide A.C. coupling to ensure that the biasing of consecutive stages of transistors do not get affected by the individual biased conditions.

10. If \(\frac{1}{2}\)µ_{n}C_{ox}*(W/L) = K and λ=0 for the C.S. stage shown below, what is the voltage gain (ideally)?

a) (R_{2} || R_{3} || R_{4}) * 3K * (V_{1} – 2V_{th})

b) (R_{2} || R_{3} || R_{4}) * K * (V_{1} + V_{th})

c) (R_{2} || R_{3} || R_{4}) * 2K * (V_{1} – V_{th})

d) (R_{2} || R_{3} || R_{4}) * K * (V_{1} – V_{th})

View Answer

Explanation: Ideally, the bypass capacitor would short the source terminal of the M

_{1}to ground. Hence, this becomes a simple C.S. stage instead of a degenerated C.S. stage. Hence, the gain is simply g

_{m}*(total resistance connected at the drain). The total resistance connected at the drain is (R

_{2}|| R

_{3}|| R

_{4}) since all the three resistors are parallel to each other. The transconductance(g

_{m}) is K(V

_{1}-V

_{th}). Hence the overall voltage gain is (R

_{2}|| R

_{3}|| R

_{4}) * K * (V

_{1}– V

_{th}).

**Sanfoundry Global Education & Learning Series – Analog Circuits.**

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