This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Storage Elements-1”.
1. Which clock is preferred in storage devices?
a) single phase overlapping clock signal
b) single phase non overlapping clock signal
c) two phase overlapping clock signal
d) two phase non overlapping clock signal
View Answer
Explanation: Two phase non-overlapping clock signal is easily available and works better and effectively and this clock will be used throughout storage system.
2. Clock signal Φ2 is to
a) write data
b) read data
c) refresh data
d) store data
View Answer
Explanation: Bits or data written into storage elements may be assumed to be settled before the immediately following signal Φ2 refreshes stored data where appropriate.
3. Data is read
a) before Φ1
b) after Φ1
c) before Φ2
d) after Φ2
View Answer
Explanation: Bits or data may be read from storage elements on the next of Φ1 clock signal that is read signals RD are Anded with Φ1.
4. Factor for assessment of storage elements are
a) volatility
b) non volatility
c) number of bits
d) data repeatability
View Answer
Explanation: Some of the comparative assessment factor for storage elements are area requirement, estimated dissipation per bit stored and volatility.
5. Which occupies lesser area?
a) nMOS
b) pMOS
c) CMOS
d) BiCMOS
View Answer
Explanation: nMOS design with buried contacts needs lesser area than CMOS design and this can be estimated by calculating space stored by each bit in register cell.
6. In which design, dissipation is less?
a) nMOS
b) pMOS
c) CMOS
d) BiCMOS
View Answer
Explanation: In CMOS design, static dissipation is very small since only the switching dissipation will be significant particularly at high speeds.
7. The impedance of pull down transistor in nMOS can be given as
a) 2Rs
b) 4Rs
c) 1/2 Rs
d) 1/4 Rs
View Answer
Explanation: Each inverter stage has 8:1 ratio and in nMOS register cell, atleast one inverter should always be on and Zp.u. is given as 4Rs and Zp.d. is given as 1/2Rs.
8. Data storage time is
a) 1 milli second
b) 1 second
c) 1 minute
d) 10 seconds
View Answer
Explanation: Data is stored by the charge on the gate capacitance of each inverter stage, so that data storage time is limited to 1 msec or less.
9. A bit is read at T1 when
a) RD is low, WR is low
b) RD is high, WR is low
c) RD is low, WR is high
d) RD is high, WR is high
View Answer
Explanation: With RD control line low, a bit can be read through clock period T1 when WR is made high. After reading the bit WR is made low.
10. A bit can be stored when
a) RD is low, WR is low
b) RD is high, WR is low
c) RD is low, WR is high
d) RD is high, WR is high
View Answer
Explanation: A bit value is stored for some time by Cg of time period T2 while both RD and WR are made low.
11. Current flows only when
a) RD is low
b) RD is high
c) RD raises exponentially high
d) RD comes exponentially down
View Answer
Explanation: Current flows only when RD is high and 1 is stored. Thus static dissipating is nil.
Sanfoundry Global Education & Learning Series – VLSI.
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