This set of VLSI online quiz focuses on “Pseudo-Random Test Patterns-2”.
1. Pseudo random testing can determine test length.
Explanation: Pseudo ramdom testing can also determine the relationship between test confidence, fault coverage, fault detectability and test length can also be determined.
2. The pseudo-random testing has
a) high cost
b) less development time
c) low cost but more testing time
d) low cost and less testing time
Explanation: Pseudo random testing method has less development time and low development cost. This can be balanced with increased test length.
3. In pseudo-random testing, the test length should be ________ the exhaustive test
a) lesser than
b) greater than
c) more than
d) none of the mentioned
Explanation: In pseudo-random testing, the test length should be less than that of the exhaustive test (its upper bound) or the test length will be prohibited for most circuits. This makes the pseudo-random testing practical.
4. Pseudo-random testing method involves
a) homogeneous bernoulli process
b) non homogeneous bernoulli process
c) repeatable bernoulli process
d) non repeatable bernoulli process
Explanation: The most accurate method invlolved in test pattern generation is non homogeneous bernoulli process. This is called as pseudo random testing method.
5. Which method is more accurate?
a) pseudo-random testing
b) random testing
d) cellular automata
Explanation: Pseudo-random testing method gives more accurate results than random testing method. Its test length estimation is smaller and test quality is better.
6. The fault coverage in a pseudo random test is determined using
a) fault detection
b) fault removal
c) fault simulation
d) fault distribution
Explanation: The fault coverage in a pseudo random test can be determined by using fault simulation. The fault coverage is the the measure used to rate the algorithmically generated tst set.
7. Faults causing largest loss of coverage is those with
a) smallest detectability
b) largest detectability
c) all of the mentioned
d) none of the mentioned
Explanation: Faults causing largest loss of coverage is those with smallest detectability. These faults are counted in the initial nonzero elements of the detectability profile.
8. With test sequence of length zero, fault coverage is
d) cannot be determined
Explanation: With test sequence of length zero, the fault coverage is 0 and each fault is responsible for fault coverage loss regardless of its detectability.
9. Upper bound fault is the fault with detectability
Explanation: Upper bound fault is the fault with detectability k=1 and it is used where the detectability profile of the circuit under test is unknown.
10. To reduce the size mismatch, test length is minimized.
Explanation: If the size of pseudo-random test generator does not match with the size of circuit under test, size mismatch occurs. This can be comprimised by reducing the test length.
Sanfoundry Global Education & Learning Series – VLSI.
To practice all areas of VLSI for online Quizzes, here is complete set of 1000+ Multiple Choice Questions and Answers.