VLSI Questions and Answers – nMOS and Complementary MOS (CMOS)

This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “nMOS and Complementary MOS (CMOS)”.

1. The n-MOS invertor is better than BJT in terms of:
a) Fast switching time
b) Low power loss
c) Smaller overall layout area
d) All the mentioned
View Answer

Answer: d
Explanation: The n-MOS invertor is better than BJT invertor due to fast switching time, low power loss, smaller overall layout area.

2. The n-MOS invertor consists of n-MOS transistor as driven and
a) Resistor as a load
b) Depletion mode n-MOS as a load
c) Enhancement mode n-MOS as a load
d) Any of the mentioned
View Answer

Answer: d
Explanation: The n-MOS inverter consists of n-MOS and resistor or depletion mode n-MOS or enhancement mode n-MOS at the pull up load.

3. If the n-MOS and p-MOS of the CMOS inverters are interchanged the output is measured at:
a) Source of both transistor
b) Drains of both transistor
c) Drain of n-MOS and source of p-MOS
d) Source of n-MOS and drain of p-MOS
View Answer

Answer: a
Explanation: When the transistors are interchanged, The drain of n-MOS is connected to supply voltage, drain of p-MOS is connected to the ground. The output is measured at source of both the transistors.
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4. What will be the effect on output voltage if the positions of n-MOS and p-MOS in CMOS inverter circuit are exchanged?
a) Output is same
b) Output is reversed
c) Output is always high
d) Output is always low
View Answer

Answer: b
Explanation: When the input is low, p-MOS is ON and the output is pulled down to the ground. When the input is high, n-MOS is ON and the output is pulled up to the supply voltage.

5. The average power dissipated in resistive load n-MOS inverter is:
a) 0
b) VDD (VDD-VOL)/R
c) VDD (VDD-VOL)/2R
d) VDD (VDD-VIH)/2R
View Answer

Answer: c
Explanation: When the input voltage is equal to VOH on the other hand, both the driver MOSFET and the load resistor conduct a nonzero current. Since the output voltage in this case is equal to VOL, DC power consumption of the inverter can be estimated as VDD (VDD-VOL)/2R.

6. The depletion mode n-MOS as an active load is better than enhancement load n-MOS in:
a) Sharp VTC transition and better noise margins
b) Single power supply
c) Smaller overall layout area
d) All of the mentioned
View Answer

Answer: d
Explanation: The depletion mode n-MOS transistor as load requires single power supply, smaller overall layout area, and sharp VTC transition.

7. The enhancement mode n-MOS load inverter requires 2 different supply voltages to:
a) Keep load transistor in cutoff region
b) Keep load transistor in linear region
c) Keep load transistor in saturation region
d) None of the mentioned
View Answer

Answer: b
Explanation: The enhancement mode n-MOS load inverter requires 2 different supply voltages to keep load transistor in linear region.
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8. The CMOS inverter consists of:
a) Enhancement mode n-MOS transistor and depletion mode p-MOS transistor
b) Enhancement mode p-MOS transistor and depletion mode n-MOS transistor
c) Enhancement mode p-MOS transistor and enhancement mode p-MOS transistor
d) Enhancement mode p-MOS transistor and enhancement mode n-MOS transistor
View Answer

Answer: d
Explanation: The CMOS inverter consist of enhancement mode p-MOS and enhancement mode n-MOS.

9. In the CMOS inverter the output voltage is measured across:
a) Drain of n-MOS transistor and ground
b) Source of p-MOS transistor and ground
c) Source of n-MOS transistor and source of p-MOS transistor
d) Gate of p-MOS transistor and Gate of n-MOS transistor
View Answer

Answer: a
Explanation: In the CMOS inverter the output voltage is measured across Drain of n-MOS transistor and ground.
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10. When the input of the CMOS inverter is equal to Inverter Threshold Voltage Vth, the transistors are operating in:
a) N-MOS is cutoff, p-MOS is in Saturation
b) P-MOS is cutoff, n-MOS is in Saturation
c) Both the transistors are in linear region
d) Both the transistors are in saturation region
View Answer

Answer: d
Explanation: When the input of the CMOS inverter is equal to Inverter Threshold Voltage Vth, both the transistors are operating in saturation region

11. The switching threshold voltage VTH for an ideal inverter is equal to:
a) (VDD-VOL)/2
b) VDD
c) (VDD)/2
d) 0
View Answer

Answer: c
Explanation: The switching threshold voltage VTH for an ideal inverter is equal to (VDD)/2.

12. Which of these invertors is more efficient?
Find the efficient invertors
a) Depletion mode n-MOS inverter
The efficient invertors - option a
b) pMOS inverter
The efficient invertors - option b
c) CMOS inverter
The efficient invertors - option c
d) Resistive load nMOS inverter
View Answer

Answer: c
Explanation: The power loss in CMOS inverter is very small and the I-V characteristics is approximately equal to ideal inverter. Therefore the CMOS inverter is most efficient.

Sanfoundry Global Education & Learning Series – VLSI.

To practice all areas of VLSI, here is complete set of 1000+ Multiple Choice Questions and Answers.

If you find a mistake in question / option / answer, kindly take a screenshot and email to [email protected]

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Manish Bhojasia - Founder & CTO at Sanfoundry
Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He lives in Bangalore, and focuses on development of Linux Kernel, SAN Technologies, Advanced C, Data Structures & Alogrithms. Stay connected with him at LinkedIn.

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