This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Design of ALU Subsystem “.
1. Design gives a detailed
a) logic circuit design
b) topology of communication
c) colour codes of the layers
d) functions of layers
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Explanation: Design is largely a matter of topology of communication rather than the detailed logic circuit design.
2. To minimize the design effort, regularity should be
a) low
b) high
c) very low
d) very high
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Explanation: Regularity is a qualitative parameter and it should be high as possible to minimize the design effort required for any system.
3. Regularity is the ratio of
a) total transistors in the chip to total transistors that must be designed in detail
b) total transistors that must be designed in detail to total transistors in a chip
c) total transistors to total components
d) total charge storage components to charge dissipating components
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Explanation: Regularity is the ratio of total transistors in the chip to total transistors that must be designed in detail.
4. Good design system has regularity in the range of
a) 25-50
b) 50-75
c) 50-100
d) 25-50
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Explanation: Good design system must have regularity in the range of 50 to 100 or more and regular structures such as memories achieve very high figures.
5. In the adder, sum is stored in
a) series
b) cascade
c) parallel
d) registers
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Explanation: The sum is stored in parallel at the output of the adder from where it may be fed through the shifter and back to the register array.
6. The shifter must be connected to
a) 2-shift data line
b) 2-shift control line
c) 4-shift data line
d) 4-shift control line
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Explanation: The shifter is unclocked but must be connected to 4 shift control lines. Carry out and Carry in signal must also be connected.
7. What is the sum and carry if the two bit number is 1 1 and the previous carry is 0?
a) 0, 0
b) 0, 1
c) 1, 0
d) 1, 1
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Explanation: If the two bit number is 1 1 and the previous carry is 0 the sum is 0 and carry is 1. This can be obtained by first adding the two numbers 1 and 1. Sum will be 0 and carry is 1. Later add the previous carry 0 to it. Now the sum is finally 0 and final carry will be 1.
8. Which design is preferred in n-bit adder?
a) many pass transistors in series
b) many pass transistors with suitable buffer
c) many pass transistors without suitable buffer
d) many pass transistors in parallel
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Explanation: In n-bit adder, n adder elements must be cascaded with carry out connecting to carry in. This carry chain will have more pass transistors connected in series which will give slow response. Thus suitable buffer can be used in between.
9. In adders, the previous carry can also be given by
a) propagate signal pk
b) generate signal gk
c) pk and gk
d) sk
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Explanation: In adders, the previous carry signal can also be given using propagate signal pk which is ex-or of two bits ak and bk and also using generate signal gk which is ‘and’ of ak and bk.
10. Adder using _______ technology can be used for speed improvement.
a) CMOS
b) BiCMOS
c) nMOS
d) pMOS
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Explanation: Using BiCMOS technology, speed improvement can be obtained by a factor of two over CMOS technology. This arrangement works will lower input voltage swings to achieve higher speed.
11. For carry skip adder, the minimum total propogation delay can be obtained when m is
a) sqrt(nk1/k2)
b) sqrt(2nk1/k2)
c) sqrt(2k1/nk2)
d) sqrt(nk1k2/2)
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Explanation: For carry skip adder the total propogation delay T is given by 2((n/M)-1)k1 + (M-2)k2. The minimum value of T can be obtained when m is sqrt(2nk1/k2).
12. Multiple output domino logic has
a) two cell manchester carry chain
b) three cell manchester carry chain
c) four cell manchester carry chain
d) four cell manchester carry look ahead
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Explanation: To reduce the complexity of the carry look ahead adder, a dynamic logic technique called multiple output domino logic is used. This approach consists of four cell manchester carry chain.
Sanfoundry Global Education & Learning Series – VLSI.
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