This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Basic MOS Transistors-1”.
1. Electronics are characterized by ____________
a) low cost
b) low weight and volume
c) reliability
d) all of the mentioned
View Answer
Explanation: Electronics are characterized by reliability, low power dissipation, extremely low weight and volume, low cost, can cope up with high degree of sophistication and complexity.
2. Speed power product is measured as the product of ____________
a) gate switching delay and gate power dissipation
b) gate switching delay and gate power absorption
c) gate switching delay and net gate power
d) gate power dissipation and absorption
View Answer
Explanation: Speed power product is measure in picojoules and it is the product of gate switching delay and gate power dissipation.
3. nMOS devices are formed in ____________
a) p-type substrate of high doping level
b) n-type substrate of low doping level
c) p-type substrate of moderate doping level
d) n-type substrate of high doping level
View Answer
Explanation: nMOS devices are formed in a p-type substrate of moderate doping level. nMOS devices have higher mobility and is cheaper.
4. Source and drain in nMOS device are isolated by ____________
a) a single diode
b) two diodes
c) three diodes
d) four diodes
View Answer
Explanation: The source and drain regions are formed by diffusing n-type impurity, it gives rise to depletion region which extend in more lightly doped p-region. Thus Source and drain in an nMOS device are isolated by two diodes.
5. In depletion mode, source and drain are connected by ____________
a) insulating channel
b) conducting channel
c) Vdd
d) Vss
View Answer
Explanation: In depletion mode, source and drain are connected by conducting channel but the channel can be closed by applying suitable negative voltage to the gate.
6. What is the condition for non saturated region?
a) Vds = Vgs – Vt
b) Vgs lesser than Vt
c) Vds lesser than Vgs – Vt
d) Vds greater than Vgs – Vt
View Answer
Explanation: The condition for non saturated region is Vds lesser Vgs – Vt. In non saturation region, MOSFET acts as voltage source. Varying Vds will provide a significant change in drain current.
7. In enhancement mode, device is in _________ condition.
a) conducting
b) non conducting
c) partially conducting
d) insulating
View Answer
Explanation: In enhancement mode, the device is in non conducting condition. For n-type FET, the threshold voltage is positive and p-type threshold voltage is negative.
8. What is the condition for non conducting mode?
a) Vds lesser than Vgs
b) Vgs lesser than Vds
c) Vgs = Vds = 0
d) Vgs = Vds = Vs = 0
View Answer
Explanation: In enhancement mode the device is in non conducting mode, and its condition is Vds = Vgs = Vs = 0.
9. nMOS is ____________
a) donor doped
b) acceptor doped
c) all of the mentioned
d) none of the mentioned
View Answer
Explanation: nMOS transistors are acceptor doped. Acceptor is a dopant which when added forms p-type region. Some of the accpetors are silicon, boron, aluminium etc.
10. MOS transistor structure is ____________
a) symmetrical
b) non symmetrical
c) semi symmetrical
d) pseudo symmetrical
View Answer
Explanation: MOS transistor structure is completely symmetrical with respect to source and drain.
11. pMOS is ____________
a) donor doped
b) acceptor doped
c) all of the mentioned
d) none of the mentioned
View Answer
Explanation: nMOS is acceptor doped and pMOS is donor doped devices. Acceptor doped forms p-type region and donor doped forms n-type region.
12. Inversion layer in enhancement mode consists of excess of ____________
a) positive carriers
b) negative carriers
c) both in equal quantity
d) neutral carriers
View Answer
Explanation: Inversion layer in enhancement mode consists of excess of negative carriers that is electron.
13. What is the condition for linear region?
a) Vgs lesser than Vt
b) Vgs greater than Vt
c) Vds lesser than Vgs
d) Vds greater than Vgs
View Answer
Explanation: The condition for linear region is Vgs > Vt. The power of MOS in the linear region is less. It is a power dissipating region.
14. As source drain voltage increases, channel depth ____________
a) increases
b) decreases
c) logarithmically increases
d) exponentially increases
View Answer
Explanation: As source drain voltage Vds increases, the channel depth at the drain end decreases.
Sanfoundry Global Education & Learning Series – VLSI.
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