This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Interrupts and Interrupt Service Routines”.
1. While CPU is executing a program, an interrupt exists then it
a) follows the next instruction in the program
b) jumps to instruction in other registers
c) breaks the normal sequence of execution of instructions
d) stops executing the program
Explanation: An interrupt function is to break the sequence of operation.
2. An interrupt breaks the execution of instructions and diverts its execution to
a) Interrupt service routine
b) Counter word register
c) Execution unit
d) control unit
Explanation: An interrupt transfers the control to interrupt service routine (ISR). After executing ISR, the control is transferred back again to main program.
3. While executing main program, if two or more interrupts occur, then the sequence of appearance of interrupts is called
b) nested interrupt
c) interrupt within interrupt
d) nested interrupt and interrupt within interrupt
Explanation: If an interrupt occurs while executing a program, and the processor is executing the interrupt, if one more interrupt occurs again, then it is called nested interrupt.
4. Whenever a number of devices interrupt a CPU at a time, and if the processor is able to handle them properly, it is said to have
a) interrupt handling ability
b) interrupt processing ability
c) multiple interrupt processing ability
d) multiple interrupt executing ability
Explanation: The processor if handles more devices as interrupts then it has multiple interrupt processing ability.
5. NMI stands for
a) nonmaskable interrupt
b) nonmultiple interrupt
c) nonmovable interrupt
Explanation: NMI is the acronym for nonmaskable interrupt.
7. If any interrupt request given to an input pin cannot be disabled by any means then the input pin is called
a) maskable interrupt
b) nonmaskable interrupt
c) maskable interrupt and nonmaskable interrupt
Explanation: A nonmaskable interrupt input pin is one which means that any interrupt request at NMI (nonmaskable interrupt) input cannot be masked or disabled by any means.
8. The INTR interrupt may be
c) maskable and nonmaskable
Explanation: the INTR (interrupt request) is maskable or can be disabled.
9. The Programmable interrupt controller is required to
a) handle one interrupt request
b) handle one or more interrupt requests at a time
c) handle one or more interrupt requests with a delay
d) handle no interrupt request
Explanation: If more than one interrupt request (INTR) occurs at a time, then an external chip called programmmable interrupt controller is required to handle them.
10. The INTR interrupt may be masked using the flag
a) direction flag
b) overflow flag
c) interrupt flag
d) sign flag
Explanation: If microprocessor wants to serve any interrupt then interrupt flag, IF=1. If interrupt flag, IF=0, then the processor ignores the service.
Sanfoundry Global Education & Learning Series – Microprocessors and Micro-controllers.