This set of Embedded Systems Multiple Choice Questions & Answers (MCQs) focuses on “Testing”.
1. Which of the following is a set of specially selected input patterns?
a) test pattern
b) debugger pattern
c) bit pattern
d) byte pattern
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Explanation: While testing any devices or embedded systems, we apply some selected inputs which is known as the test pattern and observe the output. This output is compared with the expected output. The test patterns are normally applied to the already manufactured systems.
2. Which is applied to a manufactured system?
a) bit pattern
b) parity pattern
c) test pattern
d) byte pattern
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Explanation: For testing any devices or embedded systems, we use some sort of selected inputs which is known as the test pattern and observe the output and is compared with the expected output. These test patterns are normally applied to the manufactured systems.
3. Which of the following is based on fault models?
a) alpha-numeric pattern
b) test pattern
c) bit pattern
d) parity pattern
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Explanation: The test pattern generation is normally based on the fault models and this model is also known as the stuck-at model. The test pattern is based on a certain assumption, that is why it is called the stuck-at model.
4. Which is also called stuck-at model?
a) byte pattern
b) parity pattern
c) bit pattern
d) test pattern
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Explanation: The test pattern generation is basically based on the fault models and this type of model is also known as the stuck-at model. These test patterns are based on a certain assumption, hence it is known as the stuck-at model.
5. How is the quality of the test pattern evaluated?
a) fault coverage
b) test pattern
c) size of the test pattern
d) number of errors
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Explanation: The quality of the test pattern can be evaluated on the basis of the fault coverage. It is the percentage of potential faults that can be found for a given test pattern set, that is fault coverage equals the number of detectable faults for a given test pattern set divided by the number of faults possible due to the fault model.
6. What is DfT?
a) discrete Fourier transform
b) discrete for transaction
c) design for testability
d) design Fourier transform
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Explanation: The design of testability or DfT is the process of designing for the better testability.
7. Which of the following is also known as boundary scan?
a) test pattern
b) JTAG
c) FSM
d) CRC
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Explanation: The JTAG is a technique for connecting scan chains of several chips and is also known as boundary scan.
8. What does BILBO stand for?
a) built-in logic block observer
b) bounded input bounded output
c) built-in loading block observer
d) built-in local block observer
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Explanation: The BILBO or the built-in logic block observer is proposed as a circuit combining, test response compaction, test pattern generation, and serial input/output capabilities.
9. What is CRC?
a) code reducing check
b) counter reducing check
c) counting redundancy check
d) cyclic redundancy check
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Explanation: The CRC or the cyclic redundancy check is the error detecting code which is commonly used in the storage device and the digital networks.
10. What is FSM?
a) Fourier state machine
b) finite state machine
c) fast state machine
d) free state machine
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Explanation: The FSM is the finite state machine. It will be having a finite number of states and is used to design both the sequential logic circuit and the computer programs. It can be used for testing the scan design in the testing techniques.
11. Which of the following have flip-flops which are connected to form shift registers?
a) scan design
b) test pattern
c) bit pattern
d) CRC
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Explanation: All the flip-flop storing states are connected to form a shift register in the scan design. It is a kind of test path.
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