Embedded Systems Questions and Answers – Size of Cache

This set of Embedded Systems Multiple Choice Questions & Answers (MCQs) focuses on “Size of Cache”.

1. Which of the following cache has a separate comparator for each entry?
a) direct mapped cache
b) fully associative cache
c) 2-way associative cache
d) 16-way associative cache
View Answer

Answer: b
Explanation: A fully associative cache have a comparator for each entry so that all the entries can be tested simultaneously.

2. What is the disadvantage of a fully associative cache?
a) hardware
b) software
c) memory
d) peripherals
View Answer

Answer: a
Explanation: The major disadvantage of the fully associative cache is the amount of hardware needed for the comparison increases in proportion to the cache size and hence, limits the fully associative cache.

3. How many comparators present in the direct mapping cache?
a) 3
b) 2
c) 1
d) 4
View Answer

Answer: c
Explanation: The direct mapping cache have only one comparator so that only one location possibly have all the data irrespective of the cache size.
advertisement
advertisement

4. Which mapping of cache is inefficient in software viewpoint?
a) fully associative
b) 2 way associative
c) 16 way associative
d) direct mapping
View Answer

Answer: d
Explanation: The direct mapping cache organization is simple from the hardware design aspects but it is inefficient in the software viewpoint.

5. Which mechanism splits the external memory storage into memory pages?
a) index mechanism
b) burst mode
c) distributive mode
d) a software mechanism
View Answer

Answer: a
Explanation: The index mechanism splits the external memory storage into a series of memory pages in which each page is the same size as the cache. Each page is mapped to the cache so that each page can have its own location in the cache.

6. Which of the following cache mapping can prevent bus thrashing?
a) fully associative
b) direct mapping
c) n way set associative
d) 2 way associative
View Answer

Answer: c
Explanation: Only one data can be accessed in direct mapping that is, if one word is accessed at a time, all other words are discarded at the same time. This is known as bus thrashing which can be solved by splitting up the caches so there are 2,4,..n possible entries available. The major advantage of the set associative cache is its capability to prevent the bus thrashing at the expense of hardware.

7. Which cache mapping have a sequential execution?
a) direct mapping
b) fully associative
c) n way set associative
d) burst fill
View Answer

Answer: d
Explanation: The burst fill mode of cache mapping have a sequential nature of executing instructions and data access. The instruction fetches and execution accesses to sequential memory locations until it has a jump instruction or a branch instruction. This kind of cache mapping is seen in the MC68030 processor.
advertisement

8. Which address is used for a tag?
a) memory address
b) logical address
c) cache address
d) location address
View Answer

Answer: b
Explanation: The cache memory uses either a physical address or logical address for its tag data. For a logical cache, the tag refers to a logical address and for a physical cache, the tag refers to the physical address.

9. In which of the following the data is preserved within the cache?
a) logical cache
b) physical cache
c) unified cache
d) harvard cache
View Answer

Answer: b
Explanation: In the physical cache, the data is preserved within the cache because it does not flush out during the context switching but on the other hand, the logical cache flushes out the data and clear it during a context switching.
advertisement

10. What is the disadvantage of the physical address?
a) debugging
b) delay
c) data preservation
d) data cleared
View Answer

Answer: b
Explanation: The physical address access the data through the memory management unit which causes a delay.

11. Which cache memory solve the cache coherency problem?
a) physical cache
b) logical cache
c) unified cache
d) harvard cache
View Answer

Answer: a
Explanation: The physical cache is more efficient and can provide the cache coherency problem solved and MMU delay is kept to a minimum. PowerPC is an example for this advantage.

12. What type of cache is used in the Intel 80486DX?
a) logical
b) physical
c) harvard
d) unified
View Answer

Answer: d
Explanation: The Intel 80486DX processor has a unified cache. Similarly, Motorola MPC601PC also uses the unified cache. The unified cache has the same mechanism to store both data and instructions.

13. Which of the following has a separate cache for the data and instructions?
a) unified
b) harvard
c) logical
d) physical
View Answer

Answer: b
Explanation: The Harvard cache have a separate cache for the data and the instruction whereas the unified cache has a same cache for the data and instructions.

14. Which type of cache is used the SPARC architecture?
a) unified
b) harvard
c) logical
d) physical
View Answer

Answer: c
Explanation: The SPARC architecture uses logical cache whereas most of the internal cache designed now, uses physical cache because data is not flushed out in this cache.

15. Which of the following approach uses more silicon area?
a) unified
b) harvard
c) logical
d) physical
View Answer

Answer: b
Explanation: The Harvard architecture have a separate bus for data and instruction, therefore, it requires more area. It also uses more silicon area for the second set of tags and the comparators.

Sanfoundry Global Education & Learning Series – Embedded System.

To practice all areas of Embedded System, here is complete set of 1000+ Multiple Choice Questions and Answers.

If you find a mistake in question / option / answer, kindly take a screenshot and email to [email protected]

advertisement
advertisement
Subscribe to our Newsletters (Subject-wise). Participate in the Sanfoundry Certification contest to get free Certificate of Merit. Join our social networks below and stay updated with latest contests, videos, internships and jobs!

Youtube | Telegram | LinkedIn | Instagram | Facebook | Twitter | Pinterest
Manish Bhojasia - Founder & CTO at Sanfoundry
Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He lives in Bangalore, and focuses on development of Linux Kernel, SAN Technologies, Advanced C, Data Structures & Alogrithms. Stay connected with him at LinkedIn.

Subscribe to his free Masterclasses at Youtube & discussions at Telegram SanfoundryClasses.