This set of Embedded Systems Multiple Choice Questions & Answers (MCQs) focuses on “RISC Exceptions”.
1. What does MSR stand for?
a) machine state register
b) machine software register
c) minimum state register
d) maximum state register
View Answer
Explanation: The MSR is a machine state register. When the exception is recognised, the address of the instruction and the MSR are stored in the supervisor registers while handling an exception.
2. How many supervisor registers are associated with the exception mode?
a) 2
b) 3
c) 4
d) 5
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Explanation: When the exception is recognised, the address of the instruction and the machine state register(MSR) are stored in the supervisor registers in the exception mode. There are two supervisor registers SRR0 and SRR1.
3. What happens when an exception is completed?
a) TRAP instruction executes
b) SWI instruction executes
c) RFI instruction executes
d) terminal count increases
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Explanation: When an exception is recognised, the address of the instruction and the MSR are stored in the supervisor registers and the processor moves to the supervisor mode and starts to execute the handler which is associated with the vector table. The handler examines the DSISR and FPSCR registers and carries out the required function. When it gets completed the RFI or return-from-interrupt instruction is executed.
4. How many general types of exceptions are there?
a) 2
b) 3
c) 6
d) 4
View Answer
Explanation: There are four general types of exceptions. They are synchronous precise, asynchronous precise, synchronous imprecise and asynchronous imprecise.
5. In which of the exceptions does the external event causes the exception?
a) synchronous exception
b) asynchronous exception
c) precise
d) imprecise
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Explanation: The asynchronous exception is the one in which an external event causes an exception and is independent of the instruction flow. On the other hand, the synchronous exceptions are synchronised, that is, it is caused by the instruction flow.
6. Which of the exceptions are usually a catastrophic failure?
a) imprecise exception
b) precise exception
c) synchronous exception
d) asynchronous exception
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Explanation: An imprecise exception is a catastrophic failure in which the processor cannot continue processing or allow a particular task or program to continue.
7. Which of the exceptions allows the system reset or memory fault?
a) imprecise exception
b) precise exception
c) synchronous exception
d) asynchronous exception
View Answer
Explanation: The system reset or memory fault falls into the category of imprecise exceptions while accessing the vector table.
8. Which registers are used to determine the completion status?
a) MSR
b) flag register
c) DSISR
d) index register
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Explanation: The completion status can be determined by the information bits in the DSISR and FPSCR registers.
9. Which of the following does not support PowerPC architecture?
a) synchronous precise
b) asynchronous precise
c) synchronous imprecise
d) asynchronous imprecise
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Explanation: The synchronous imprecise is usually not supported on the PowerPC architecture and also in the MPC601, MPC603 etc.
10. Which exceptions are used in the PowerPC for floating point?
a) synchronous imprecise
b) asynchronous imprecise
c) synchronous precise
d) synchronous imprecise
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Explanation: The PowerPC can handle the floating point exception by making use of the synchronous imprecise mode.
11. Which exception is used in the external interrupts and decrementer-caused exceptions?
a) synchronous precise
b) asynchronous precise
c) synchronous imprecise
d) asynchronous imprecise
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Explanation: The asynchronous precise type exception is used to handle the external interrupts and decrementer-caused exceptions. Both these can occur at any time within the instruction flow.
12. Which exception can be masked by clearing the EE bit to zero in the MSR?
a) synchronous imprecise
b) synchronous precise
c) asynchronous imprecise
d) asynchronous precise
View Answer
Explanation: The asynchronous precise type exceptions can be masked by clearing the EE bits in the MSR. This bit is automatically cleared to zero in the MSR in order to prevent this interrupt causing an exception while other exceptions are being processed.
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