This set of Embedded Systems Multiple Choice Questions & Answers (MCQs) focuses on “The Mechanism of Interrupts”.
1. Which of the following uses clock edge to generate an interrupt?
a) edge triggered
b) level-triggered
c) software interrupt
d) nmi
View Answer
Explanation: In the edge-triggered interrupt, the clock edge is used to generate an interrupt. The transition is from a logical low to high or vice versa.
2. In which interrupt, the trigger is dependent on the logic level?
a) edge triggered
b) level-triggered
c) software interrupt
d) nmi
View Answer
Explanation: In the level-triggered interrupt, the trigger is completely dependent on the logic level. The processors may require the level to be in a certain clock width so that the shorter pulses which are shorter than the minimum pulse width are ignored.
3. At which point the processor will start to internally process the interrupt?
a) interrupt pointer
b) instruction pointer
c) instruction boundary
d) interrupt boundary
View Answer
Explanation: After the recognition of the interrupt, and finds that it is not an error condition with the currently executing interrupt, then the interrupt will not be internally executed until the current execution has completed. This point is known as the instruction boundary. At this point, the processor will start to internally process the interrupt.
4. What does 80×86 use to hold essential data?
a) stack frame
b) register
c) internal register
d) flag register
View Answer
Explanation: The MC68000 and 80×86 family use stack frame for holding the data whereas RISC processors use special internal registers.
5. What does the RISC processor use to hold the data?
a) flag register
b) accumulator
c) internal register
d) stack register
View Answer
Explanation: The RISC processors uses special internal registers to hold data whereas the 80×86 and MC68000 family uses stack register to hold the data.
6. Which of the following is a stack-based processor?
a) MC68000
b) PowerPC
c) ARM
d) DEC Alpha
View Answer
Explanation: The MC68000, Intel 80×86 and most of the b-bit controllers are based on the stack-based processors whereas PowerPC, DEC alpha, and ARM are RISC families which have a special internal register for holding the data.
7. Which of the following is used to reduce the external memory cycle?
a) internal hardware stack
b) internal software stack
c) external software stack
d) internal register
View Answer
Explanation: Some of the processors use internal hardware stack which helps in reducing the external memory cycle necessary to store the stack frame.
8. How many interrupt levels are supported in the MC68000?
a) 2
b) 3
c) 4
d) 7
View Answer
Explanation: The MC68000 has an external stack for holding the data. The MC68000 family supports a seven interrupt level which are encoded into three interrupt pins.
9. How many interrupt pins are used in MC68000?
a) 2
b) 3
c) 4
d) 5
View Answer
Explanation: The MC68000 family supports a seven interrupt level which are encoded into three interrupt pins. These interrupt pins are IP0, IP1, and IP2.
10. Which priority encoder is used in MC68000?
a) 4-to-2 priority encoder
b) LS148 7-to-3
c) 2-to-4 priority encoder
d) LS148 3-to-7
View Answer
Explanation: The LS148 7-to-3 priority encoder is used in MC68000. This converts the seven external pins into a three-bit binary code.
11. Which of the following converts the seven external pins into a 3-bit binary code?
a) priority encoder
b) 4-to-2 priority encoder
c) LS148 7-to-3
d) 2-to-4 priority encoder
View Answer
Explanation: The LS148 7-to-3 priority encoder can convert the seven external pins into a three-bit binary code.
12. Which of the following ensures the recognition of the interrupt?
a) interrupt ready
b) interrupt acknowledge
c) interrupt terminal
d) interrupt start
View Answer
Explanation: The interrupt level remains asserted until its interrupt acknowledgment cycle ensures the recognition of the interrupt.
13. Which of the following is raised to the interrupt level to prevent the multiple interrupt request?
a) internal interrupt mask
b) external interrupt mask
c) non-maskable interrupt
d) software interrupt
View Answer
Explanation: The internal interrupt mask is raised to the interrupt level, in order to prevent the multiple interrupt acknowledgments.
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