This set of Embedded Systems Multiple Choice Questions & Answers (MCQs) focuses on “DRAM Interfaces”.
1. In which pin does the data appear in the basic DRAM interfacing?
a) dout pin
b) din pin
c) clock
d) interrupt pin
View Answer
Explanation: In the basic DRAM interfacing, the higher order bits asserts the RAS signal and the lower order bits asserts the CAS signal. When the access got expired, the data appears on the dout pin and is latched by the processor.
2. What is the duration for memory refresh to remain compatible?
a) 20 microseconds
b) 12 microseconds
c) 15 microseconds
d) 10 microseconds
View Answer
Explanation: The memory refresh is performed every 15 microseconds in order to remain compatible.
3. Which interfacing method lowers the speed of the processor?
a) basic DRAM interface
b) page mode interface
c) page interleaving
d) burst mode interface
View Answer
Explanation: The direct method access limits the wait state-free operation which lowers the processor speed.
4. What is EDO RAM?
a) extreme data operation
b) extended direct operation
c) extended data out
d) extended DRAM out
View Answer
Explanation: EDO RAM is a special kind of random access memory which can improve the time to read from the memory on faster microprocessors. The example of such a microprocessor is Intel Pentium.
5. What is RDRAM?
a) refresh DRAM
b) recycle DRAM
c) Rambus DRAM
d) refreshing DRAM
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Explanation: Rambus DRAM is a synchronous memory developed by Rambus. It can replace SDRAM and is useful in high bandwidth applications.
6. Which of the following can transfer up to 1.6 billion bytes per second?
a) DRAM
b) RDRAM
c) EDO RAM
d) SDRAM
View Answer
Explanation: The Rambus RAM can transfer up to 1.6 billion bytes per second. It possesses RAM controller, a bus which connects the microprocessor and the device, and random access memory.
7. Which of the following cycle is larger than the access time?
a) write cycle
b) set up time
c) read cycle
d) hold time
View Answer
Explanation: The read cycle in the DRAM interfacing is larger than the access time because of the precharge time.
8. Which mode of operation selects an internal page of memory in the DRAM interfacing?
a) page interleaving
b) page mode
c) burst mode
d) EDO RAM
View Answer
Explanation: In the page mode operation, the row address is provided as normal but the RAS signal is left asserted. This, in turn, selects an internal page within the DRAM memory where any bit of data can be accessed by placing the column address and asserting CAS.
9. What is the maximum time that the RAS signal can be asserted in the page mode operation?
a) 5 microseconds
b) 10 microseconds
c) 15 microseconds
d) 20 microseconds
View Answer
Explanation: The maximum time that the RAS signal can be asserted during the page mode operation is about 10 microseconds. But this is a major disadvantage for page mode operation, that is, the standard PCs have a maximum time of 15 microseconds for the refresh cycle.
10. Which of the following mode of operation in the DRAM interfacing has a page boundary?
a) burst mode
b) EDO RAM
c) page mode
d) page interleaving
View Answer
Explanation: The page mode operation have memory cycles that exhibit some form of locality, that is, stay within the page boundary which causes page missing when there is access outside the page boundary and two or more wait states.
11. Which mode offers the banking of memory in the DRAM interfacing technique?
a) page mode
b) basic DRAM interfacing
c) page interleaving
d) burst mode
View Answer
Explanation: The accessing of data outside the page boundary can cause missing of pages in the page mode operation. So a program has to operate for frequently accessing data thereby, increasing the efficiency in the page selection. One such mode is the page interleaving mode in which the memory is divided into different banks, depending on the number of memories installed.
12. Which of the following has a fast page mode RAM?
a) burst mode
b) page interleaving
c) EDO memory
d) page mode
View Answer
Explanation: Extended data out memory is a fast page mode RAM which has a faster cycling process which makes EDO memory a faster page mode access.
13. Which mode reduces the need for fast static RAMs?
a) page mode
b) page interleaving
c) burst mode
d) EDO memory
View Answer
Explanation: The page mode, nibble mode devices can provide data fastly when the new column address is given. In burst mode operation, the processor can fetch more data than it needs and keeps the remaining data in an internal cache for the future use which can reduce the need for fast static RAMs.
14. Which of the following is also known as hyper page mode enabled DRAM?
a) page mode
b) EDO DRAM
c) burst EDO DRAM
d) page interleaving
View Answer
Explanation: The EDO DRAM is also known as hyper page mode enable DRAM because of the faster page mode operation along with some additional features.
15. What does BEDO DRAM stand for?
a) burst EDO DRAM
b) buffer EDO DRAM
c) BIBO EDO DRAM
d) bilateral EDO DRAM
View Answer
Explanation: The burst EDO DRAM is evolved from the EDO DRAM and it can access four memory addresses in one burst. It also supports pipeline stages which allow the page access cycle into two parts.
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